drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
104
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
112
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
120
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
128
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
29
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
37
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
45
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
53
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
62
struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
63
struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
80
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
88
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
96
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
drivers/gpu/drm/xe/regs/xe_engine_regs.h
100
#define CS_MMIO_GROUP_INSTANCE_SELECT(base) XE_REG((base) + 0xcc)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
115
#define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
120
#define CS_DEBUG_MODE2(base) XE_REG((base) + 0xd8, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
123
#define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
126
#define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
130
#define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
132
#define RING_BBADDR(base) XE_REG((base) + 0x140)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
133
#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
135
#define PR_CTR_CTRL(base) XE_REG((base) + 0x178)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
141
#define PR_CTR_THRSH(base) XE_REG((base) + 0x17c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
143
#define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
147
#define BLIT_CCTL(base) XE_REG((base) + 0x204)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
151
#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
152
#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
154
#define RING_IDLEDLY(base) XE_REG((base) + 0x23c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
158
#define RING_CURRENT_LRCA(base) XE_REG((base) + 0x240)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
160
#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
168
#define GFX_MODE(base) XE_REG((base) + 0x29c, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
172
#define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
175
#define RING_QUEUE_TIMESTAMP(base) XE_REG((base) + 0x4c0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
176
#define RING_QUEUE_TIMESTAMP_UDW(base) XE_REG((base) + 0x4c0 + 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
178
#define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
180
#define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
184
#define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
185
#define RING_CTX_TIMESTAMP_UDW(base) XE_REG((base) + 0x3ac)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
186
#define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
188
#define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
206
#define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
207
#define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
209
#define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
212
#define CS_CHICKEN1(base) XE_REG((base) + 0x580, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
220
#define CS_GPR_DATA(base, n) XE_REG((base) + 0x600 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
224
#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
227
#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
231
#define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
234
#define VDBOX_CGCTL3F1C(base) XE_REG((base) + 0x3f1c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
46
#define ENGINE_ID(base) XE_REG((base) + 0x8c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
50
#define RING_TAIL(base) XE_REG((base) + 0x30)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
53
#define RING_HEAD(base) XE_REG((base) + 0x34)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
56
#define RING_START(base) XE_REG((base) + 0x38)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
58
#define RING_CTL(base) XE_REG((base) + 0x3c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
61
#define RING_START_UDW(base) XE_REG((base) + 0x48)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
63
#define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
68
#define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
71
#define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
72
#define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
73
#define RING_IPEHR(base) XE_REG((base) + 0x68)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
74
#define RING_INSTDONE(base) XE_REG((base) + 0x6c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
75
#define RING_ACTHD(base) XE_REG((base) + 0x74)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
76
#define RING_DMA_FADD(base) XE_REG((base) + 0x78)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
77
#define RING_HWS_PGA(base) XE_REG((base) + 0x80)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
78
#define RING_HWSTAM(base) XE_REG((base) + 0x98)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
79
#define RING_MI_MODE(base) XE_REG((base) + 0x9c)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
80
#define RING_NOPID(base) XE_REG((base) + 0x94)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
82
#define FF_THREAD_MODE(base) XE_REG((base) + 0xa0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
85
#define RING_INT_SRC_RPT_PTR(base) XE_REG((base) + 0xa4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
86
#define RING_IMR(base) XE_REG((base) + 0xa8)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
87
#define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
89
#define CS_INT_VEC(base) XE_REG((base) + 0x1b8)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
91
#define RING_EIR(base) XE_REG((base) + 0xb0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
92
#define RING_EMR(base) XE_REG((base) + 0xb4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
93
#define RING_ESR(base) XE_REG((base) + 0xb8)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
95
#define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
98
#define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
25
#define HECI_H_CSR(base) XE_REG((base) + 0x4)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
36
#define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
41
#define HECI_FWSTS2(base) XE_REG((base) + 0xc48)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
42
#define HECI_FWSTS3(base) XE_REG((base) + 0xc60)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
43
#define HECI_FWSTS4(base) XE_REG((base) + 0xc64)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
44
#define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
46
#define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
48
#define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
51
#define GSCI_TIMER_STATUS XE_REG(0x11ca28)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
101
#define VE1_AUX_INV XE_REG(0x42b8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
110
#define XE2_LMEM_CFG XE_REG(0x48b0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
113
#define XE2_GAMWALK_CTRL_MEDIA XE_REG(XE2_GAMWALK_CTRL + MEDIA_GT_GSI_OFFSET)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
146
#define FF_MODE2 XE_REG(0x6604)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
158
#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
162
#define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
173
#define SC_INSTDONE XE_REG(0x7100)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
174
#define SC_INSTDONE_EXTRA XE_REG(0x7104)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
175
#define SC_INSTDONE_EXTRA2 XE_REG(0x7108)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
181
#define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
187
#define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
199
#define XE2LPM_CCCHKNREG1 XE_REG(0x82a8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
20
#define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
201
#define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
204
#define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
207
#define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
211
#define XELPMP_SQCNT1 XE_REG(0x8718)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
226
#define GSCPSMI_BASE XE_REG(0x880c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
233
#define XEHP_FUSE4 XE_REG(0x9114)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
238
#define MIRROR_FUSE3 XE_REG(0x9118)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
249
#define MIRROR_FUSE1 XE_REG(0x911c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
251
#define FUSE2 XE_REG(0x9120)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
254
#define MIRROR_L3BANK_ENABLE XE_REG(0x9130)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
257
#define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */
drivers/gpu/drm/xe/regs/xe_gt_regs.h
259
#define XELP_GT_SLICE_ENABLE XE_REG(0x9138)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
26
#define RPM_CONFIG0 XE_REG(0xd00)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
260
#define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
262
#define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
266
#define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
267
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
268
#define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
269
#define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
270
#define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
271
#define XE3P_XPC_GT_GEOMETRY_DSS_3 XE_REG(0x915c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
272
#define XE3P_XPC_GT_COMPUTE_DSS_3 XE_REG(0x9160)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
274
#define SERVICE_COPY_ENABLE XE_REG(0x9170)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
277
#define GDRST XE_REG(0x941c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
281
#define MISCCPCTL XE_REG(0x9424)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
284
#define UNSLCGCTL9430 XE_REG(0x9430)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
287
#define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
295
#define UNSLCGCTL9440 XE_REG(0x9440)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
309
#define UNSLCGCTL9444 XE_REG(0x9444)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
327
#define UNSLCGCTL9454 XE_REG(0x9454)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
339
#define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
34
#define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
35
#define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
355
#define RPNSWREQ XE_REG(0xa008)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
358
#define RP_CONTROL XE_REG(0xa024)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
36
#define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
362
#define RC_CONTROL XE_REG(0xa090)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
366
#define RC_STATE XE_REG(0xa094)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
367
#define RC_IDLE_HYSTERSIS XE_REG(0xa0ac)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
368
#define MEDIA_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
369
#define RENDER_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
371
#define PMINTRMSK XE_REG(0xa168)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
375
#define FORCEWAKE_GT XE_REG(0xa188)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
377
#define POWERGATE_ENABLE XE_REG(0xa210)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
38
#define GMD_ID XE_REG(0xd8c)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
384
#define FORCEWAKE_RENDER XE_REG(0xa278)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
386
#define POWERGATE_DOMAIN_STATUS XE_REG(0xa2a0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
394
#define MISC_STATUS_0 XE_REG(0xa500)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
396
#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
397
#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
398
#define FORCEWAKE_GSC XE_REG(0xa618)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
400
#define XELP_GARBCNTL XE_REG(0xb004)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
407
#define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
463
#define XE2_GLOBAL_INVAL XE_REG(0xb404)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
473
#define XE2_TDF_CTRL XE_REG(0xb418)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
480
#define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
482
#define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
49
#define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
496
#define LMEM_CFG XE_REG(0xcf58)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
50
#define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
52
#define STEER_SEMAPHORE XE_REG(0xfd0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
53
#define MTL_MCR_SELECTOR XE_REG(0xfd4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
54
#define SF_MCR_SELECTOR XE_REG(0xfd8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
55
#define MCR_SELECTOR XE_REG(0xfdc)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
56
#define GAM_MCR_SELECTOR XE_REG(0xfe0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
599
#define MAIN_GAMCTRL_MODE XE_REG(0xef00)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
602
#define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
612
#define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
619
#define FORCEWAKE_ACK_GT XE_REG(0x130044)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
626
#define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
627
#define MTL_MEDIA_MC6 XE_REG(0x138048)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
629
#define GT_CORE_STATUS XE_REG(0x138060)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
634
#define GT_GFX_RC6_LOCKED XE_REG(0x138104)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
635
#define GT_GFX_RC6 XE_REG(0x138108)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
637
#define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
65
#define PS_INVOCATION_COUNT XE_REG(0x2348)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
661
#define GT_PERF_STATUS XE_REG(0x1381b4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
664
#define SFC_DONE(n) XE_REG(0x1cc000 + (n) * 0x1000)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
67
#define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
96
#define CCS_AUX_INV XE_REG(0x4208)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
98
#define VD0_AUX_INV XE_REG(0x4218)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
99
#define VE0_AUX_INV XE_REG(0x4238)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
101
#define GUC_INTR_CHICKEN XE_REG(0xc50c)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
104
#define GUC_BCS_RCS_IER XE_REG(0xc550)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
105
#define GUC_VCS2_VCS1_IER XE_REG(0xc554)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
106
#define GUC_WD_VECS_IER XE_REG(0xc558)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
107
#define GUC_PM_P24C_IER XE_REG(0xc55c)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
109
#define GUC_TLB_INV_CR XE_REG(0xcee8)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
112
#define HUC_STATUS2 XE_REG(0xd3b0)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
115
#define GT_PM_CONFIG XE_REG(0x13816c)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
118
#define GUC_HOST_INTERRUPT XE_REG(0x1901f0, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
120
#define VF_SW_FLAG(n) XE_REG(0x190240 + (n) * 4, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
123
#define MED_GUC_HOST_INTERRUPT XE_REG(0x190304, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
125
#define MED_VF_SW_FLAG(n) XE_REG(0x190310 + (n) * 4, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
128
#define GUC_TLB_INV_CR XE_REG(0xcee8)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
130
#define PVC_GUC_TLB_INV_DESC0 XE_REG(0xcf7c)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
132
#define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
16
#define DIST_DBS_POPULATED XE_REG(0xd08)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
20
#define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
22
#define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
24
#define GTCR XE_REG(0x4274)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
27
#define GUC_ARAT_C6DIS XE_REG(0xa178)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
29
#define GUC_STATUS XE_REG(0xc000)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
43
#define BOOT_HASH_CHK XE_REG(0xc010)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
46
#define GUC_HEADER_INFO XE_REG(0xc014)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
48
#define GUC_WOPCM_SIZE XE_REG(0xc050)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
52
#define GUC_SHIM_CONTROL XE_REG(0xc064)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
63
#define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
66
#define HUC_KERNEL_LOAD_INFO XE_REG(0xc1dc)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
69
#define UOS_RSA_SCRATCH(i) XE_REG(0xc200 + (i) * 4)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
72
#define DMA_ADDR_0_LOW XE_REG(0xc300)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
73
#define DMA_ADDR_0_HIGH XE_REG(0xc304)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
74
#define DMA_ADDR_1_LOW XE_REG(0xc308)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
75
#define DMA_ADDR_1_HIGH XE_REG(0xc30c)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
79
#define DMA_COPY_SIZE XE_REG(0xc310)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
80
#define DMA_CTRL XE_REG(0xc314)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
84
#define DMA_GUC_WOPCM_OFFSET XE_REG(0xc340)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
90
#define GUC_SRAM_STATUS XE_REG(0xc398)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
93
#define GUC_MAX_IDLE_COUNT XE_REG(0xc3e4)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
95
#define GUC_PMTIMESTAMP_LO XE_REG(0xc3e8)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
96
#define GUC_PMTIMESTAMP_HI XE_REG(0xc3ec)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
98
#define GUC_SEND_INTERRUPT XE_REG(0xc4c8)
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
12
#define HEC_UNCORR_FW_ERR_DW0(base) XE_REG((base) + 0x124)
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
27
#define ERR_STAT_GT_REG(x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
39
#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
50
#define ERR_STAT_GT_FATAL_VECTOR_REG(x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
57
#define ERR_STAT_GT_COR_VECTOR_REG(x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
70
#define SOC_GLOBAL_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
78
#define SOC_GSYSEVTCTL_REG(master, slave, x) XE_REG(_PICK_EVEN((x), \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
84
#define SOC_LOCAL_ERR_STAT_REG(base, hw_err) XE_REG(hw_err == HARDWARE_ERROR_CORRECTABLE ? \
drivers/gpu/drm/xe/regs/xe_hw_error_regs.h
9
#define HEC_UNCORR_ERR_STATUS(base) XE_REG((base) + 0x118)
drivers/gpu/drm/xe/regs/xe_i2c_regs.h
14
#define REG_SG_REMAP_ADDR_PREFIX XE_REG(SOC_BASE + 0x0164)
drivers/gpu/drm/xe/regs/xe_i2c_regs.h
15
#define REG_SG_REMAP_ADDR_POSTFIX XE_REG(SOC_BASE + 0x0168)
drivers/gpu/drm/xe/regs/xe_i2c_regs.h
17
#define I2C_BRIDGE_PCICFGCTL XE_REG(I2C_BRIDGE_OFFSET + 0x200)
drivers/gpu/drm/xe/regs/xe_i2c_regs.h
20
#define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND)
drivers/gpu/drm/xe/regs/xe_i2c_regs.h
21
#define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
14
#define DG1_MSTR_TILE_INTR XE_REG(0x190008)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
18
#define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
34
#define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
45
#define RENDER_COPY_INTR_ENABLE XE_REG(0x190030, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
46
#define VCS_VECS_INTR_ENABLE XE_REG(0x190034, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
47
#define GUC_SG_INTR_ENABLE XE_REG(0x190038, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
50
#define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
51
#define CRYPTO_RSVD_INTR_ENABLE XE_REG(0x190040)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
52
#define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
53
#define CCS_RSVD_INTR_ENABLE XE_REG(0x190048, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
55
#define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
65
#define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
66
#define RCS0_RSVD_INTR_MASK XE_REG(0x190090, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
67
#define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
68
#define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
69
#define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
70
#define VCS4_VCS5_INTR_MASK XE_REG(0x1900b0, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
71
#define VCS6_VCS7_INTR_MASK XE_REG(0x1900b4, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
72
#define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
73
#define VECS2_VECS3_INTR_MASK XE_REG(0x1900d4, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
74
#define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
75
#define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
76
#define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
77
#define CRYPTO_RSVD_INTR_MASK XE_REG(0x1900f0)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
78
#define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
79
#define CCS0_CCS1_INTR_MASK XE_REG(0x190100)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
80
#define CCS2_CCS3_INTR_MASK XE_REG(0x190104)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
81
#define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
82
#define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
83
#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
84
#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
21
#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
30
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
35
#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
37
#define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
40
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
drivers/gpu/drm/xe/regs/xe_mert_regs.h
11
#define MERT_LMEM_CFG XE_REG(0x1448b0)
drivers/gpu/drm/xe/regs/xe_mert_regs.h
13
#define MERT_TLB_CT_INTR_ERR_ID_PORT XE_REG(0x145190)
drivers/gpu/drm/xe/regs/xe_mert_regs.h
20
#define MERT_TLB_INV_DESC_A XE_REG(0x14cf7c)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
100
#define OAM_STATUS(base) XE_REG((base) + OAM_STATUS_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
101
#define OAM_MMIO_TRG(base) XE_REG((base) + OAM_MMIO_TRG_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
103
#define OAM_COMPRESSION_T3_CONTROL XE_REG(0x1c2e00)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
114
#define OAMERT_CONTROL XE_REG(0x1453a0)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
115
#define OAMERT_DEBUG XE_REG(0x1453a4)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
116
#define OAMERT_STATUS XE_REG(0x1453a8)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
117
#define OAMERT_HEAD_POINTER XE_REG(0x1453ac)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
118
#define OAMERT_TAIL_POINTER XE_REG(0x1453b0)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
119
#define OAMERT_BUFFER XE_REG(0x1453b4)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
12
#define RPM_CONFIG1 XE_REG(0xd04)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
120
#define OAMERT_CONTEXT_CONTROL XE_REG(0x1453c8)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
121
#define OAMERT_MMIO_TRG XE_REG(0x1453cc)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
15
#define EU_PERF_CNTL0 XE_REG(0xe458)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
16
#define EU_PERF_CNTL4 XE_REG(0xe45c)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
17
#define EU_PERF_CNTL1 XE_REG(0xe558)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
18
#define EU_PERF_CNTL5 XE_REG(0xe55c)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
19
#define EU_PERF_CNTL2 XE_REG(0xe658)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
20
#define EU_PERF_CNTL6 XE_REG(0xe65c)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
21
#define EU_PERF_CNTL3 XE_REG(0xe758)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
23
#define OA_TLB_INV_CR XE_REG(0xceec)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
26
#define OAR_OACONTROL XE_REG(0x2960)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
30
#define OACTXCONTROL(base) XE_REG((base) + 0x360)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
31
#define OAR_OASTATUS XE_REG(0x2968)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
35
#define OAG_OAGLBCTXCTRL XE_REG(0x2b28)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
40
#define OAG_OAHEADPTR XE_REG(0xdb00)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
42
#define OAG_OATAILPTR XE_REG(0xdb04)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
45
#define OAG_OABUFFER XE_REG(0xdb08)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
49
#define OAG_OACONTROL XE_REG(0xdaf4)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
62
#define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
72
#define OAG_OASTATUS XE_REG(0xdafc)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
77
#define OAG_MMIOTRIGGER XE_REG(0xdb1c)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
79
#define OAC_OACONTROL XE_REG(0x15114)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
9
#define SYS_MEM_LAT_MEASURE XE_REG(0x145194)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
94
#define OAM_HEAD_POINTER(base) XE_REG((base) + OAM_HEAD_POINTER_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
95
#define OAM_TAIL_POINTER(base) XE_REG((base) + OAM_TAIL_POINTER_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
96
#define OAM_BUFFER(base) XE_REG((base) + OAM_BUFFER_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
97
#define OAM_CONTEXT_CONTROL(base) XE_REG((base) + OAM_CONTEXT_CONTROL_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
98
#define OAM_CONTROL(base) XE_REG((base) + OAM_CONTROL_OFFSET)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
99
#define OAM_DEBUG(base) XE_REG((base) + OAM_DEBUG_OFFSET)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
15
#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
16
#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
17
#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
18
#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
19
#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
21
#define BMG_FAN_1_SPEED XE_REG(0x138140)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
22
#define BMG_FAN_2_SPEED XE_REG(0x138170)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
23
#define BMG_FAN_3_SPEED XE_REG(0x1381a0)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
24
#define BMG_VRAM_TEMPERATURE_N(n) XE_REG(0x138260 + ((n) * (sizeof(u32))))
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
25
#define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
28
#define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
30
#define CRI_PACKAGE_ENERGY_STATUS XE_REG(0x138120)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
31
#define CRI_PLATFORM_ENERGY_STATUS XE_REG(0x138458)
drivers/gpu/drm/xe/regs/xe_pmt.h
13
#define PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
drivers/gpu/drm/xe/regs/xe_pxp_regs.h
14
#define KCR_INIT XE_REG(0x3860f0)
drivers/gpu/drm/xe/regs/xe_pxp_regs.h
18
#define KCR_SIP XE_REG(0x386260)
drivers/gpu/drm/xe/regs/xe_pxp_regs.h
21
#define KCR_GLOBAL_TERMINATE XE_REG(0x3860f8)
drivers/gpu/drm/xe/regs/xe_regs.h
12
#define GU_CNTL_PROTECTED XE_REG(0x10100C)
drivers/gpu/drm/xe/regs/xe_regs.h
15
#define GU_CNTL XE_REG(0x101010)
drivers/gpu/drm/xe/regs/xe_regs.h
19
#define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
drivers/gpu/drm/xe/regs/xe_regs.h
22
#define GU_DEBUG XE_REG(0x101018)
drivers/gpu/drm/xe/regs/xe_regs.h
25
#define VIRTUAL_CTRL_REG XE_REG(0x10108c)
drivers/gpu/drm/xe/regs/xe_regs.h
28
#define XEHP_MTCFG_ADDR XE_REG(0x101800)
drivers/gpu/drm/xe/regs/xe_regs.h
31
#define GGC XE_REG(0x108040)
drivers/gpu/drm/xe/regs/xe_regs.h
35
#define DSMBASE XE_REG(0x1080C0)
drivers/gpu/drm/xe/regs/xe_regs.h
38
#define GSMBASE XE_REG(0x108100)
drivers/gpu/drm/xe/regs/xe_regs.h
40
#define STOLEN_RESERVED XE_REG(0x1082c0)
drivers/gpu/drm/xe/regs/xe_regs.h
43
#define SG_TILE_ADDR_RANGE(_idx) XE_REG(0x1083a0 + (_idx) * 4)
drivers/gpu/drm/xe/regs/xe_regs.h
45
#define MTL_RP_STATE_CAP XE_REG(0x138000)
drivers/gpu/drm/xe/regs/xe_regs.h
47
#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
drivers/gpu/drm/xe/regs/xe_regs.h
48
#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
drivers/gpu/drm/xe/regs/xe_regs.h
50
#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
drivers/gpu/drm/xe/regs/xe_regs.h
54
#define MTL_MPA_FREQUENCY XE_REG(0x138028)
drivers/gpu/drm/xe/regs/xe_regs.h
57
#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
drivers/gpu/drm/xe/regs/xe_regs.h
60
#define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF)
drivers/gpu/drm/xe/regs/xe_regs.h
63
#define PVC_RP_STATE_CAP XE_REG(0x281014)
drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
10
#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
16
#define SYSCTRL_MB_CTRL XE_REG(0x10)
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
26
#define SYSCTRL_MB_DATA0 XE_REG(0x14)
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
27
#define SYSCTRL_MB_DATA1 XE_REG(0x18)
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
28
#define SYSCTRL_MB_DATA2 XE_REG(0x1c)
drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
29
#define SYSCTRL_MB_DATA3 XE_REG(0x20)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
26
#define REGULAR_REG1 XE_REG(1)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
27
#define REGULAR_REG2 XE_REG(2)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
28
#define REGULAR_REG3 XE_REG(3)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
29
#define REGULAR_REG4 XE_REG(4)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
30
#define BAD_REGULAR_REG5 XE_REG(5)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
36
#define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
39
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
drivers/gpu/drm/xe/xe_guc_capture.c
384
ext->reg = XE_REG(extlist->reg.__reg.addr);
drivers/gpu/drm/xe/xe_guc_pc.c
42
#define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
drivers/gpu/drm/xe/xe_guc_pc.c
47
#define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
drivers/gpu/drm/xe/xe_guc_pc.c
51
#define GT_PERF_STATUS XE_REG(0x1381b4)
drivers/gpu/drm/xe/xe_hwmon.c
330
return XE_REG(0);
drivers/gpu/drm/xe/xe_i2c.c
261
*val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET));
drivers/gpu/drm/xe/xe_i2c.c
270
xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val);
drivers/gpu/drm/xe/xe_irq.c
34
#define IMR(offset) XE_REG(offset + 0x4)
drivers/gpu/drm/xe/xe_irq.c
35
#define IIR(offset) XE_REG(offset + 0x8)
drivers/gpu/drm/xe/xe_irq.c
36
#define IER(offset) XE_REG(offset + 0xc)
drivers/gpu/drm/xe/xe_nvm.c
51
return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &
drivers/gpu/drm/xe/xe_oa.c
2301
oa_regs[i].addr = XE_REG(addr);
drivers/gpu/drm/xe/xe_pat.c
335
struct xe_reg reg = XE_REG(_PAT_INDEX(i));
drivers/gpu/drm/xe/xe_pat.c
341
xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
drivers/gpu/drm/xe/xe_pat.c
344
xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), pta_entry->value);
drivers/gpu/drm/xe/xe_pat.c
378
u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
drivers/gpu/drm/xe/xe_pat.c
456
pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
drivers/gpu/drm/xe/xe_pat.c
514
pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
drivers/gpu/drm/xe/xe_pat.c
527
pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA));
drivers/gpu/drm/xe/xe_pat.c
535
pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_ATS));
drivers/gpu/drm/xe/xe_pcode_api.h
105
#define BMG_PCIE_CAP XE_REG(0x138340)
drivers/gpu/drm/xe/xe_pcode_api.h
13
#define PCODE_MAILBOX XE_REG(0x138124)
drivers/gpu/drm/xe/xe_pcode_api.h
28
#define PCODE_DATA0 XE_REG(0x138128)
drivers/gpu/drm/xe/xe_pcode_api.h
29
#define PCODE_DATA1 XE_REG(0x13812C)
drivers/gpu/drm/xe/xe_pcode_api.h
89
#define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
drivers/gpu/drm/xe/xe_reg_whitelist.c
21
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
drivers/gpu/drm/xe/xe_reg_whitelist.c
73
XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
drivers/gpu/drm/xe/xe_reg_whitelist.c
76
WHITELIST(XE_REG(0x4500),
drivers/gpu/drm/xe/xe_tuning.c
21
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
drivers/gpu/drm/xe/xe_wa.c
128
#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
