BPF_REG_FP
if (rd != BPF_REG_FP)
if (rs != BPF_REG_FP)
if (reg != BPF_REG_FP) {
if (reg != BPF_REG_FP)
if (reg != BPF_REG_FP)
} else if (bpf_reg == BPF_REG_FP) {
usage |= BIT(REG_LO(BPF_REG_FP));
[BPF_REG_FP] = {ARC_R_FP, },
const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
[BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
const u8 fp = bpf2a64[BPF_REG_FP];
if (insn->dst_reg == BPF_REG_FP || insn->src_reg == BPF_REG_FP) {
ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_FP];
const u8 fp = bpf2a64[BPF_REG_FP];
[BPF_REG_FP] = A64_R(25),
emit_insn(ctx, addid, regmap[BPF_REG_FP], LOONGARCH_GPR_SP, bpf_stack_adjust);
[BPF_REG_FP] = LOONGARCH_GPR_S4,
[BPF_REG_FP] = {MIPS_R_FP, MIPS_R_ZERO},
[BPF_REG_FP] = {MIPS_R_ZERO, MIPS_R_FP},
const u8 *fp = bpf2mips32[BPF_REG_FP];
if (ctx->accessed & BIT(BPF_REG_FP))
if (ctx->accessed & BIT(BPF_REG_FP))
u8 fp = bpf2mips64[BPF_REG_FP];
if (ctx->accessed & BIT(BPF_REG_FP))
if (ctx->accessed & BIT(BPF_REG_FP))
[BPF_REG_FP] = MIPS_R_FP,
dst = regmap[BPF_REG_FP];
[BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
reg = regmap[BPF_REG_FP]; /* -> HPPA_REG_FP */
[BPF_REG_FP] = HPPA_R(14),
if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) {
EMIT(PPC_RAW_LI(bpf_to_ppc(BPF_REG_FP) - 1, 0));
EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1,
ctx->b2p[BPF_REG_FP] = _R18;
bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP));
bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP)) ||
PPC_LI64(bpf_to_ppc(BPF_REG_FP), (__force long)ctx->priv_sp);
EMIT(PPC_RAW_ADD(bpf_to_ppc(BPF_REG_FP),
bpf_to_ppc(TMP_REG_1), bpf_to_ppc(BPF_REG_FP)));
EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), bpf_to_ppc(BPF_REG_FP),
if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) {
EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1,
ctx->b2p[BPF_REG_FP] = _R31;
const s8 *fp = bpf2rv32[BPF_REG_FP];
[BPF_REG_FP] = {RV_REG_S6, RV_REG_S5},
[BPF_REG_FP] = RV_REG_S5,
[BPF_REG_FP] = 13,
EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15,
if (insn->dst_reg == BPF_REG_FP)
if (insn->dst_reg == BPF_REG_FP)
if (insn->dst_reg == BPF_REG_FP)
if (insn->dst_reg == BPF_REG_FP)
[BPF_REG_FP] = L6,
const u8 vfp = bpf2sparc[BPF_REG_FP];
if (insn->src_reg == BPF_REG_FP)
emit_stx(pprog, BPF_DW, BPF_REG_FP, reg, stack_off);
if (src_reg == BPF_REG_FP)
if (dst_reg == BPF_REG_FP)
[BPF_REG_FP] = 5, /* RBP readonly */
dst_reg = BPF_REG_FP;
dst_reg = BPF_REG_FP;
src_reg = BPF_REG_FP;
BIT(BPF_REG_FP));
emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP,
emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0,
emit_stx(prog, BPF_DW, BPF_REG_FP,
BPF_REG_FP,
emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off);
emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8);
emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off);
const u8 fplo = bpf2ia32[BPF_REG_FP][0];
const u8 fphi = bpf2ia32[BPF_REG_FP][1];
[BPF_REG_FP] = {STACK_OFFSET(80), STACK_OFFSET(84)},
if (sreg != BPF_REG_FP)
if (sreg != BPF_REG_FP)
for (j = 0; j < BPF_REG_FP; j++) {
#define FP regs[BPF_REG_FP]
insn_buf[cnt++] = BPF_ST_MEM(BPF_DW, BPF_REG_FP, -stack_depth,
insn_buf[cnt++] = BPF_ST_MEM(BPF_DW, BPF_REG_FP, -stack_depth + 8, 0);
insn_buf[cnt++] = BPF_ST_MEM(BPF_DW, BPF_REG_FP, -stack_depth,
insn_buf[cnt++] = BPF_STX_MEM(BPF_DW, BPF_REG_FP, BPF_REG_1,
if (reg == BPF_REG_FP) {
return regno == BPF_REG_FP || at->frame == depth ||
at_in[0][BPF_REG_FP] = arg_single(depth, 0);
if (reg == BPF_REG_FP) {
if (reg == BPF_REG_FP) {
for (i = 0; i < BPF_REG_FP; i++, state_reg++) {
for (j = 0; j < BPF_REG_FP; j++) {
for (i = 0; i < BPF_REG_FP; i++) {
for (j = 0; j < BPF_REG_FP; j++) {
regs[BPF_REG_FP].type = PTR_TO_STACK;
mark_reg_known_zero(env, regs, BPF_REG_FP);
regs[BPF_REG_FP].frameno = state->frameno;
if (regno == BPF_REG_FP)
if (regno == BPF_REG_FP) {
BPF_ALU64_REG(BPF_MOV, R3, BPF_REG_FP),
BPF_LDX_MEM(BPF_DW, R0, BPF_REG_FP, -8),
BPF_LDX_MEM(BPF_DW, R0, BPF_REG_FP, -16),
BPF_STX_MEM(BPF_DW, BPF_REG_FP, R0, -8),
BUILD_BUG_ON(BPF_REG_FP + 1 != MAX_BPF_REG);
*insn = BPF_STX_MEM(BPF_W, BPF_REG_FP, BPF_CLASS(fp->code) ==
BPF_REG_A : BPF_REG_X, BPF_REG_FP,
*insn++ = BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_FP, ctx_stack_off);
__imm_insn(fp1_u8_st_zero, BPF_ST_MEM(BPF_B, BPF_REG_FP, -1, 0)),
__imm_insn(fp10_u16_st_zero, BPF_ST_MEM(BPF_H, BPF_REG_FP, -10, 0)),
__imm_insn(fp18_u16_st_zero, BPF_ST_MEM(BPF_H, BPF_REG_FP, -18, 0))
__imm_insn(fp8_st_zero, BPF_ST_MEM(BPF_DW, BPF_REG_FP, -8, 0))
__imm_insn(fp4_st_zero, BPF_ST_MEM(BPF_W, BPF_REG_FP, -4, 0))
__imm_insn(fp8_st_one, BPF_ST_MEM(BPF_DW, BPF_REG_FP, -8, 1))
__imm_insn(fp8_st_one, BPF_ST_MEM(BPF_W, BPF_REG_FP, -8, 1)) /* 32-bit spill */
*insn++ = BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_FP, ctx_stack_off);
*insn++ = BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_FP, ctx_stack_off);
BPF_STX_MEM(BPF_DW, BPF_REG_FP, BPF_REG_0, -24),
BPF_STX_MEM(BPF_DW, BPF_REG_FP, BPF_REG_0, -32),
BPF_MOV64_REG(BPF_REG_1, BPF_REG_FP),
BPF_MOV64_REG(BPF_REG_2, BPF_REG_FP),
BPF_MOV64_REG(BPF_REG_2, BPF_REG_FP),
BPF_MOV64_REG(BPF_REG_1, BPF_REG_FP),
BPF_MOV64_REG(BPF_REG_2, BPF_REG_FP),
BPF_ST_MEM(BPF_DW, BPF_REG_FP, -8, 0),
BPF_MOV64_REG(BPF_REG_2, BPF_REG_FP),
BPF_MOV64_REG(BPF_REG_2, BPF_REG_FP),
BPF_ST_MEM(BPF_DW, BPF_REG_FP, -8, 0),
BPF_MOV64_REG(BPF_REG_1, BPF_REG_FP),