XA_LIMIT
XA_LIMIT(AMDXDNA_INVALID_CTX_HANDLE + 1, MAX_HWCTX_ID),
XA_LIMIT(0, MAX_MSG_ID_ENTRIES - 1),
XA_LIMIT(0, NUM_HEAP_MINORS - 1), GFP_KERNEL);
ret = xa_alloc(&fw_device_xa, &minor, device, XA_LIMIT(0, MINORMASK), GFP_KERNEL);
XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL);
_t == DRM_MINOR_ACCEL ? XA_LIMIT(0, ACCEL_MAX_MINORS) : XA_LIMIT(64 * _t, 64 * _t + 63); \
#define DRM_EXTENDED_MINOR_LIMIT XA_LIMIT(192, (1 << MINORBITS) - 1)
XA_LIMIT(0, MAX_JM_CTX_PER_FILE), GFP_KERNEL);
XA_LIMIT(0, MAX_HEAPS_PER_POOL - 1), GFP_KERNEL);
XA_LIMIT(1, PANTHOR_MAX_VMS_PER_FILE), GFP_KERNEL);
ret = xa_alloc(&gpool->xa, &gid, group, XA_LIMIT(1, MAX_GROUPS_PER_POOL), GFP_KERNEL);
err = xa_alloc(&fpriv->contexts, &args->context, context, XA_LIMIT(1, U32_MAX),
err = xa_alloc(&context->mappings, &args->mapping, mapping, XA_LIMIT(1, U32_MAX),
XA_LIMIT(XE_MAX_ASID - 2, XE_MAX_ASID - 1),
XA_LIMIT(1, XE_MAX_GROUP_SIZE - 1), GFP_KERNEL);
limit = (dynamic_msix) ? XA_LIMIT(NUM_OF_STATIC_MSIX, xe->irq.msix.nvec - 1) :
XA_LIMIT(*msix, *msix);
XA_LIMIT(1, XE_MAX_ASID - 1),
mad_agent_priv, XA_LIMIT(0, (1 << 24) - 1),
XA_LIMIT(1, dev->attrs.max_qp - 1),
XA_LIMIT(1, dev->attrs.max_cq - 1),
XA_LIMIT(0, IONIC_MAX_QPID),
struct xa_limit limit = XA_LIMIT(1, SIW_STAG_MAX_INDEX);
XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
ret = xa_alloc(&ice_aux_id, &pf->aux_idx, NULL, XA_LIMIT(1, INT_MAX),
status = xa_alloc(&pi->sched_node_ids, &new_node->id, NULL, XA_LIMIT(0, UINT_MAX),
err = xa_alloc(&ctx->xarray, &mi->id, mi, XA_LIMIT(1, ctx->max_id),
XA_LIMIT(1, MLX5_POST_ACTION_MAX), GFP_KERNEL);
XA_LIMIT(1, MLX5_MACEC_RX_FS_ID_MAX), GFP_KERNEL);
XA_LIMIT(1, ESW_IPSEC_RX_MAPPED_ID_MASK), 0);
XA_LIMIT(0, NFP_NET_IPSEC_MAX_SA_CNT - 1), GFP_KERNEL);
ret = xa_alloc(&pse_pw_d_map, &index, pw_d, XA_LIMIT(1, PSE_PW_D_LIMIT),
ret = xa_alloc(&opp_configs, &id, data, XA_LIMIT(1, INT_MAX),
#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
XA_LIMIT(1, USHRT_MAX), GFP_KERNEL);
if (xa_alloc(&udev->commands, &cmd_id, tcmu_cmd, XA_LIMIT(1, 0xffff),
XA_LIMIT(QCOMTEE_OBJECT_ID_START,
limit = XA_LIMIT(0, CONFIG_SERIAL_LITEUART_MAX_PORTS);
limit = XA_LIMIT(dev_id, dev_id);
XA_LIMIT(1, INT_MAX),
#define xa_limit_32b XA_LIMIT(0, UINT_MAX)
#define xa_limit_31b XA_LIMIT(0, INT_MAX)
#define xa_limit_16b XA_LIMIT(0, USHRT_MAX)
#define PP_DMA_INDEX_LIMIT XA_LIMIT(1, BIT(PP_DMA_INDEX_BITS) - 1)
XA_LIMIT(0, USHRT_MAX), &ctx->pers_next, GFP_KERNEL);
struct xa_limit limit = XA_LIMIT(1, 0x3fff);
XA_LIMIT(5, 10), GFP_KERNEL) != 0);
XA_LIMIT(5, 10), GFP_KERNEL) != 0);
XA_LIMIT(UINT_MAX - 1, UINT_MAX),
XA_LIMIT(UINT_MAX - 1, UINT_MAX),
XA_LIMIT(UINT_MAX - 1, UINT_MAX),
XA_BUG_ON(xa, xa_alloc(xa, &id, xa_mk_index(10), XA_LIMIT(10, 5),
XA_BUG_ON(xa, xa_alloc(xa, &id, xa_mk_index(10), XA_LIMIT(10, 5),
XA_LIMIT(1, MEM_CGROUP_ID_MAX), GFP_KERNEL);
XA_LIMIT(1, limit - 1), GFP_KERNEL_ACCOUNT);
XA_LIMIT(1, limit - 1), GFP_KERNEL_ACCOUNT);
XA_LIMIT(QRTR_MIN_EPH_SOCKET, QRTR_MAX_EPH_SOCKET)
XA_LIMIT(min, max), GFP_KERNEL);
XA_LIMIT(AA_FIRST_SECID, INT_MAX), gfp);