BMCR_SPEED1000
BMCR_FULLDPLX | BMCR_SPEED1000, bmcr);
BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX,
bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
new_bmcr |= BMCR_SPEED1000;
BMCR_SPEED1000);
bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
BMCR_FULLDPLX | BMCR_SPEED1000);
bmcr |= BMCR_SPEED1000;
switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
case BMCR_SPEED1000:
bmcr &= ~BMCR_SPEED1000;
new_bmcr |= BMCR_SPEED1000;
bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
bmcr |= BMCR_SPEED1000;
ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
ctl |= BMCR_SPEED1000;
if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
#ifndef BMCR_SPEED1000
ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
ctl |= BMCR_SPEED1000;
if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
if (bmcr & BMCR_SPEED1000)
if (bmcr & BMCR_SPEED1000)
switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
case BMCR_SPEED1000:
BMCR_SPEED1000);
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
ctl |= BMCR_SPEED1000;
if (bmcr & BMCR_SPEED1000)
phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
*phy_ctrl &= ~BMCR_SPEED1000;
*phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
BMCR_SPEED1000 | BMCR_FULLDPLX);
(val & BMCR_SPEED1000))
phylink |= ((bmcr & BMCR_SPEED1000) &&
mii_ctrl |= BMCR_SPEED1000;
bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
bmcr |= BMCR_SPEED1000;
bmcr |= BMCR_SPEED1000;
MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
((bmcr & BMCR_SPEED1000 &&
cmd->base.speed = ((bmcr & BMCR_SPEED1000 &&
BMCR_SPEED1000 | BMCR_FULLDPLX);
tmp |= BMCR_SPEED1000;
BMCR_SPEED1000 | BMCR_FULLDPLX);
tmp |= BMCR_SPEED1000;
speed &= BMCR_SPEED100 | BMCR_SPEED1000;
if (speed == BMCR_SPEED1000)
BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100,
BMCR_SPEED1000);
BMCR_SPEED1000)
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
BMCR_SPEED1000 | BMCR_SPEED100,
BMCR_SPEED1000);
BMCR_SPEED1000 | BMCR_SPEED100,
BMCR_SPEED1000 | BMCR_SPEED100,
BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
mscr2_ctl = BMCR_SPEED1000;
MII_88E1510_MSCR_2, BMCR_SPEED1000 |
BMCR_SPEED1000 | BMCR_FULLDPLX |
BMCR_SPEED1000 | BMCR_FULLDPLX);
BMCR_SPEED1000 | BMCR_FULLDPLX);
temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
if (val & BMCR_SPEED1000)
err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
BMCR_SPEED1000);
if (bmcr & BMCR_SPEED1000)
mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
BMCR_SPEED1000 | BMCR_FULLDPLX);
#define XILINX_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
val |= BMCR_SPEED1000;
bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
bmcr = BMCR_SPEED1000;
#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)