arch/arc/include/asm/hugepage.h
17
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
arch/arc/include/uapi/asm/page.h
31
#define PAGE_OFFSET _AC(0x80000000, UL) /* Kernel starts at 2G onwrds */
arch/arm/include/asm/cp15.h
111
#define cr_alignment UL(0)
arch/arm/include/asm/delay.h
41
#define UDELAY_MULT UL(2147 * HZ + 483648 * HZ / 1000000)
arch/arm/include/asm/efi.h
74
#define EFI_PHYS_ALIGN max(UL(SZ_2M), roundup_pow_of_two(TEXT_OFFSET))
arch/arm/include/asm/kasan_def.h
75
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/arm/include/asm/kasan_def.h
76
#define KASAN_SHADOW_END ((UL(1) << (32 - KASAN_SHADOW_SCALE_SHIFT)) \
arch/arm/include/asm/memory.h
113
#define TASK_SIZE UL(0xffffffff)
arch/arm/include/asm/memory.h
116
#define TASK_UNMAPPED_BASE UL(0x00000000)
arch/arm/include/asm/memory.h
120
#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
arch/arm/include/asm/memory.h
146
#define ITCM_OFFSET UL(0xfffe0000)
arch/arm/include/asm/memory.h
147
#define DTCM_OFFSET UL(0xfffe8000)
arch/arm/include/asm/memory.h
156
#define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
arch/arm/include/asm/memory.h
34
#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
arch/arm/include/asm/memory.h
44
#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
arch/arm/include/asm/memory.h
53
#define TASK_SIZE_26 (UL(1) << 26)
arch/arm/include/asm/memory.h
86
#define FDT_FIXED_BASE UL(0xff800000)
arch/arm/include/asm/memory.h
97
#define VECTORS_BASE UL(0xffff0000)
arch/arm/include/asm/pgtable-3level.h
58
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
arch/arm/mach-davinci/hardware.h
23
#define IO_PHYS UL(0x01c00000)
arch/arm/mach-omap1/usb.c
527
#define OMAP1510_LB_OFFSET UL(0x30000000)
arch/arm/mach-spear/spear.h
18
#define SPEAR_ICM1_2_BASE UL(0xD0000000)
arch/arm/mach-spear/spear.h
20
#define SPEAR_ICM1_UART_BASE UL(0xD0000000)
arch/arm/mach-spear/spear.h
22
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
arch/arm/mach-spear/spear.h
25
#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
arch/arm/mach-spear/spear.h
29
#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
arch/arm/mach-spear/spear.h
31
#define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
arch/arm/mach-spear/spear.h
32
#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
arch/arm/mach-spear/spear.h
34
#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000)
arch/arm/mach-spear/spear.h
46
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
arch/arm/mach-spear/spear.h
51
#define PERIP_GRP2_BASE UL(0xB3000000)
arch/arm/mach-spear/spear.h
53
#define MCIF_SDHCI_BASE UL(0xB3000000)
arch/arm/mach-spear/spear.h
54
#define SYSRAM0_BASE UL(0xB3800000)
arch/arm/mach-spear/spear.h
58
#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear.h
60
#define UART_BASE UL(0xE0000000)
arch/arm/mach-spear/spear.h
62
#define SSP_BASE UL(0xE0100000)
arch/arm/mach-spear/spear.h
63
#define MISC_BASE UL(0xE0700000)
arch/arm/mach-spear/spear.h
66
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
arch/arm/mach-spear/spear.h
69
#define SPEAR1310_RAS_BASE UL(0xD8400000)
arch/arm/mach-spear/spear.h
70
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
arch/arm/mach-spear/spear.h
73
#define A9SM_PERIP_BASE UL(0xEC800000)
arch/arm/mach-spear/spear.h
77
#define L2CC_BASE UL(0xED000000)
arch/arm/mach-spear/spear.h
78
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
arch/arm/mach-spear/spear.h
81
#define MCIF_CF_BASE UL(0xB2800000)
arch/arm/mach-spear/spear1310.c
21
#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
arch/arm/mach-spear/spear1310.c
22
#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
arch/arm/mach-spear/spear310.c
20
#define SPEAR310_UART1_BASE UL(0xB2000000)
arch/arm/mach-spear/spear310.c
21
#define SPEAR310_UART2_BASE UL(0xB2080000)
arch/arm/mach-spear/spear310.c
22
#define SPEAR310_UART3_BASE UL(0xB2100000)
arch/arm/mach-spear/spear310.c
23
#define SPEAR310_UART4_BASE UL(0xB2180000)
arch/arm/mach-spear/spear310.c
24
#define SPEAR310_UART5_BASE UL(0xB2200000)
arch/arm/mach-spear/spear320.c
22
#define SPEAR320_UART1_BASE UL(0xA3000000)
arch/arm/mach-spear/spear320.c
23
#define SPEAR320_UART2_BASE UL(0xA4000000)
arch/arm/mach-spear/spear320.c
24
#define SPEAR320_SSP0_BASE UL(0xA5000000)
arch/arm/mach-spear/spear320.c
25
#define SPEAR320_SSP1_BASE UL(0xA6000000)
arch/arm64/include/asm/cputype.h
12
#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
arch/arm64/include/asm/esr.h
100
#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/esr.h
104
#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT)
arch/arm64/include/asm/esr.h
106
#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
arch/arm64/include/asm/esr.h
108
#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
arch/arm64/include/asm/esr.h
110
#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
arch/arm64/include/asm/esr.h
112
#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
arch/arm64/include/asm/esr.h
13
#define ESR_ELx_EC_UNKNOWN UL(0x00)
arch/arm64/include/asm/esr.h
14
#define ESR_ELx_EC_WFx UL(0x01)
arch/arm64/include/asm/esr.h
148
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
arch/arm64/include/asm/esr.h
150
#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
arch/arm64/include/asm/esr.h
152
#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
arch/arm64/include/asm/esr.h
154
#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
arch/arm64/include/asm/esr.h
156
#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
arch/arm64/include/asm/esr.h
158
#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
arch/arm64/include/asm/esr.h
16
#define ESR_ELx_EC_CP15_32 UL(0x03)
arch/arm64/include/asm/esr.h
160
#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
arch/arm64/include/asm/esr.h
164
#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
arch/arm64/include/asm/esr.h
166
#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
arch/arm64/include/asm/esr.h
168
#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
arch/arm64/include/asm/esr.h
17
#define ESR_ELx_EC_CP15_64 UL(0x04)
arch/arm64/include/asm/esr.h
170
#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
arch/arm64/include/asm/esr.h
172
#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
arch/arm64/include/asm/esr.h
177
#define ESR_ELx_CV (UL(1) << 24)
arch/arm64/include/asm/esr.h
179
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
arch/arm64/include/asm/esr.h
18
#define ESR_ELx_EC_CP14_MR UL(0x05)
arch/arm64/include/asm/esr.h
180
#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
arch/arm64/include/asm/esr.h
181
#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
arch/arm64/include/asm/esr.h
182
#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
arch/arm64/include/asm/esr.h
183
#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
arch/arm64/include/asm/esr.h
184
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
arch/arm64/include/asm/esr.h
185
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
arch/arm64/include/asm/esr.h
186
#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
arch/arm64/include/asm/esr.h
19
#define ESR_ELx_EC_CP14_LS UL(0x06)
arch/arm64/include/asm/esr.h
195
#define DISR_EL1_IDS (UL(1) << 24)
arch/arm64/include/asm/esr.h
20
#define ESR_ELx_EC_FP_ASIMD UL(0x07)
arch/arm64/include/asm/esr.h
21
#define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
arch/arm64/include/asm/esr.h
213
#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
arch/arm64/include/asm/esr.h
219
#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
arch/arm64/include/asm/esr.h
22
#define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
arch/arm64/include/asm/esr.h
221
#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
arch/arm64/include/asm/esr.h
223
#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
arch/arm64/include/asm/esr.h
225
#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
arch/arm64/include/asm/esr.h
227
#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
arch/arm64/include/asm/esr.h
229
#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
arch/arm64/include/asm/esr.h
23
#define ESR_ELx_EC_OTHER UL(0x0A)
arch/arm64/include/asm/esr.h
25
#define ESR_ELx_EC_CP14_64 UL(0x0C)
arch/arm64/include/asm/esr.h
26
#define ESR_ELx_EC_BTI UL(0x0D)
arch/arm64/include/asm/esr.h
27
#define ESR_ELx_EC_ILL UL(0x0E)
arch/arm64/include/asm/esr.h
29
#define ESR_ELx_EC_SVC32 UL(0x11)
arch/arm64/include/asm/esr.h
30
#define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
arch/arm64/include/asm/esr.h
31
#define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
arch/arm64/include/asm/esr.h
326
#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
arch/arm64/include/asm/esr.h
33
#define ESR_ELx_EC_SVC64 UL(0x15)
arch/arm64/include/asm/esr.h
336
#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
arch/arm64/include/asm/esr.h
338
#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
arch/arm64/include/asm/esr.h
34
#define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
arch/arm64/include/asm/esr.h
340
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
arch/arm64/include/asm/esr.h
342
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
arch/arm64/include/asm/esr.h
344
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
arch/arm64/include/asm/esr.h
35
#define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
arch/arm64/include/asm/esr.h
36
#define ESR_ELx_EC_SYS64 UL(0x18)
arch/arm64/include/asm/esr.h
362
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
arch/arm64/include/asm/esr.h
365
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
arch/arm64/include/asm/esr.h
368
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
arch/arm64/include/asm/esr.h
37
#define ESR_ELx_EC_SVE UL(0x19)
arch/arm64/include/asm/esr.h
370
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
arch/arm64/include/asm/esr.h
38
#define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
arch/arm64/include/asm/esr.h
40
#define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
arch/arm64/include/asm/esr.h
402
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
arch/arm64/include/asm/esr.h
403
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
arch/arm64/include/asm/esr.h
404
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
arch/arm64/include/asm/esr.h
405
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
arch/arm64/include/asm/esr.h
406
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
arch/arm64/include/asm/esr.h
407
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
arch/arm64/include/asm/esr.h
408
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
arch/arm64/include/asm/esr.h
41
#define ESR_ELx_EC_SME UL(0x1D)
arch/arm64/include/asm/esr.h
43
#define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
arch/arm64/include/asm/esr.h
44
#define ESR_ELx_EC_IABT_LOW UL(0x20)
arch/arm64/include/asm/esr.h
45
#define ESR_ELx_EC_IABT_CUR UL(0x21)
arch/arm64/include/asm/esr.h
46
#define ESR_ELx_EC_PC_ALIGN UL(0x22)
arch/arm64/include/asm/esr.h
48
#define ESR_ELx_EC_DABT_LOW UL(0x24)
arch/arm64/include/asm/esr.h
49
#define ESR_ELx_EC_DABT_CUR UL(0x25)
arch/arm64/include/asm/esr.h
50
#define ESR_ELx_EC_SP_ALIGN UL(0x26)
arch/arm64/include/asm/esr.h
51
#define ESR_ELx_EC_MOPS UL(0x27)
arch/arm64/include/asm/esr.h
52
#define ESR_ELx_EC_FP_EXC32 UL(0x28)
arch/arm64/include/asm/esr.h
54
#define ESR_ELx_EC_FP_EXC64 UL(0x2C)
arch/arm64/include/asm/esr.h
55
#define ESR_ELx_EC_GCS UL(0x2D)
arch/arm64/include/asm/esr.h
57
#define ESR_ELx_EC_SERROR UL(0x2F)
arch/arm64/include/asm/esr.h
58
#define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
arch/arm64/include/asm/esr.h
59
#define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
arch/arm64/include/asm/esr.h
60
#define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
arch/arm64/include/asm/esr.h
61
#define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
arch/arm64/include/asm/esr.h
62
#define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
arch/arm64/include/asm/esr.h
63
#define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
arch/arm64/include/asm/esr.h
65
#define ESR_ELx_EC_BKPT32 UL(0x38)
arch/arm64/include/asm/esr.h
67
#define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
arch/arm64/include/asm/esr.h
69
#define ESR_ELx_EC_BRK64 UL(0x3C)
arch/arm64/include/asm/esr.h
71
#define ESR_ELx_EC_MAX UL(0x3F)
arch/arm64/include/asm/esr.h
75
#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
arch/arm64/include/asm/esr.h
79
#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
arch/arm64/include/asm/esr.h
88
#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
arch/arm64/include/asm/esr.h
92
#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
arch/arm64/include/asm/esr.h
94
#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/esr.h
96
#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/esr.h
97
#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/esr.h
98
#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/esr.h
99
#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
arch/arm64/include/asm/kernel-pgtable.h
28
#define SWAPPER_BLOCK_SIZE (UL(1) << SWAPPER_BLOCK_SHIFT)
arch/arm64/include/asm/kernel-pgtable.h
64
#define INIT_IDMAP_FDT_PAGES (EARLY_PAGES(INIT_IDMAP_PGTABLE_LEVELS, 0UL, UL(MAX_FDT_SIZE), 1) - 1)
arch/arm64/include/asm/kvm_arm.h
261
#define VTTBR_CNP_BIT (UL(1))
arch/arm64/include/asm/kvm_arm.h
262
#define VTTBR_VMID_SHIFT (UL(48))
arch/arm64/include/asm/kvm_arm.h
306
#define HPFAR_MASK (~UL(0xf))
arch/arm64/include/asm/memory.h
102
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/arm64/include/asm/memory.h
103
#define KASAN_SHADOW_END ((UL(1) << (64 - KASAN_SHADOW_SCALE_SHIFT)) + KASAN_SHADOW_OFFSET)
arch/arm64/include/asm/memory.h
104
#define _KASAN_SHADOW_START(va) (KASAN_SHADOW_END - (UL(1) << ((va) - KASAN_SHADOW_SCALE_SHIFT)))
arch/arm64/include/asm/memory.h
131
#define THREAD_SIZE (UL(1) << THREAD_SHIFT)
arch/arm64/include/asm/memory.h
145
#define NVHE_STACK_SIZE (UL(1) << NVHE_STACK_SHIFT)
arch/arm64/include/asm/memory.h
44
#define _PAGE_OFFSET(va) (-(UL(1) << (va)))
arch/arm64/include/asm/memory.h
51
#define VMEMMAP_END (-UL(SZ_1G))
arch/arm64/include/asm/memory.h
54
#define FIXADDR_TOP (-UL(SZ_8M))
arch/arm64/include/asm/memory.h
66
#define _PAGE_END(va) (-(UL(1) << ((va) - 1)))
arch/arm64/include/asm/mmu.h
12
#define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
arch/arm64/include/asm/mmu.h
13
#define TTBR_ASID_MASK (UL(0xffff) << 48)
arch/arm64/include/asm/mte-def.h
8
#define MTE_GRANULE_SIZE UL(16)
arch/arm64/include/asm/pgtable-hwdef.h
226
#define TTBR_CNP_BIT (UL(1) << 0)
arch/arm64/include/asm/pgtable-hwdef.h
231
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)
arch/arm64/include/asm/pgtable-hwdef.h
232
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)
arch/arm64/include/asm/pgtable-hwdef.h
291
#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
arch/arm64/include/asm/pgtable-hwdef.h
292
(UL(1) << (48 - PGDIR_SHIFT))) * 8)
arch/arm64/include/asm/pgtable-hwdef.h
56
#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
arch/arm64/include/asm/pgtable-hwdef.h
66
#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
arch/arm64/include/asm/pgtable-hwdef.h
73
#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
arch/arm64/include/asm/pgtable-hwdef.h
83
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
arch/arm64/include/asm/pgtable-prot.h
98
#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
arch/arm64/include/asm/pgtable.h
479
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
arch/arm64/include/asm/processor.h
55
#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
arch/arm64/include/asm/processor.h
56
#define TASK_SIZE_64 (UL(1) << vabits_actual)
arch/arm64/include/asm/processor.h
57
#define TASK_SIZE_MAX (UL(1) << VA_BITS)
arch/arm64/include/asm/processor.h
65
#define TASK_SIZE_32 UL(0x100000000)
arch/arm64/include/asm/processor.h
67
#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
arch/arm64/include/asm/rsi_cmds.h
16
#define RSI_GRANULE_SIZE (_AC(1, UL) << RSI_GRANULE_SHIFT)
arch/arm64/include/asm/rsi_smc.h
168
#define RSI_NO_CHANGE_DESTROYED UL(0)
arch/arm64/include/asm/rsi_smc.h
169
#define RSI_CHANGE_DESTROYED UL(1)
arch/arm64/include/asm/rsi_smc.h
171
#define RSI_ACCEPT UL(0)
arch/arm64/include/asm/rsi_smc.h
172
#define RSI_REJECT UL(1)
arch/arm64/include/asm/rsi_smc.h
21
#define RSI_ABI_VERSION_MAJOR UL(1)
arch/arm64/include/asm/rsi_smc.h
27
#define RSI_ABI_VERSION_MINOR UL(0)
arch/arm64/include/asm/rsi_smc.h
35
#define RSI_SUCCESS UL(0)
arch/arm64/include/asm/rsi_smc.h
36
#define RSI_ERROR_INPUT UL(1)
arch/arm64/include/asm/rsi_smc.h
37
#define RSI_ERROR_STATE UL(2)
arch/arm64/include/asm/rsi_smc.h
38
#define RSI_INCOMPLETE UL(3)
arch/arm64/include/asm/rsi_smc.h
39
#define RSI_ERROR_UNKNOWN UL(4)
arch/arm64/include/asm/smp.h
12
#define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1)
arch/arm64/include/asm/smp.h
23
#define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT)
arch/arm64/include/asm/smp.h
24
#define CPU_STUCK_REASON_NO_GRAN (UL(2) << CPU_STUCK_REASON_SHIFT)
arch/arm64/include/asm/sysreg.h
1008
#define POE_NONE UL(0x0)
arch/arm64/include/asm/sysreg.h
1009
#define POE_R UL(0x1)
arch/arm64/include/asm/sysreg.h
1010
#define POE_X UL(0x2)
arch/arm64/include/asm/sysreg.h
1011
#define POE_RX UL(0x3)
arch/arm64/include/asm/sysreg.h
1012
#define POE_W UL(0x4)
arch/arm64/include/asm/sysreg.h
1013
#define POE_RW UL(0x5)
arch/arm64/include/asm/sysreg.h
1014
#define POE_WX UL(0x6)
arch/arm64/include/asm/sysreg.h
1015
#define POE_RWX UL(0x7)
arch/arm64/include/asm/sysreg.h
1016
#define POE_MASK UL(0xf)
arch/arm64/include/asm/sysreg.h
873
#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
arch/arm64/include/asm/sysreg.h
874
#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
arch/arm64/include/asm/sysreg.h
875
#define MAIR_ATTR_NORMAL_NC UL(0x44)
arch/arm64/include/asm/sysreg.h
876
#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
arch/arm64/include/asm/sysreg.h
877
#define MAIR_ATTR_NORMAL UL(0xff)
arch/arm64/include/asm/sysreg.h
878
#define MAIR_ATTR_MASK UL(0xff)
arch/arm64/include/asm/sysreg.h
962
#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
arch/arm64/include/asm/sysreg.h
963
#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
arch/arm64/include/asm/sysreg.h
987
#define PIE_NONE_O UL(0x0)
arch/arm64/include/asm/sysreg.h
988
#define PIE_R_O UL(0x1)
arch/arm64/include/asm/sysreg.h
989
#define PIE_X_O UL(0x2)
arch/arm64/include/asm/sysreg.h
990
#define PIE_RX_O UL(0x3)
arch/arm64/include/asm/sysreg.h
991
#define PIE_RW_O UL(0x5)
arch/arm64/include/asm/sysreg.h
992
#define PIE_RWnX_O UL(0x6)
arch/arm64/include/asm/sysreg.h
993
#define PIE_RWX_O UL(0x7)
arch/arm64/include/asm/sysreg.h
994
#define PIE_R UL(0x8)
arch/arm64/include/asm/sysreg.h
995
#define PIE_GCS UL(0x9)
arch/arm64/include/asm/sysreg.h
996
#define PIE_RX UL(0xa)
arch/arm64/include/asm/sysreg.h
997
#define PIE_RW UL(0xc)
arch/arm64/include/asm/sysreg.h
998
#define PIE_RWX UL(0xe)
arch/arm64/include/asm/sysreg.h
999
#define PIE_MASK UL(0xf)
arch/arm64/kernel/reloc_test_core.c
38
{ "R_AARCH64_ABS64", absolute_data64, UL(SYM64_ABS_VAL) },
arch/arm64/kernel/reloc_test_core.c
39
{ "R_AARCH64_ABS32", absolute_data32, UL(SYM32_ABS_VAL) },
arch/arm64/kernel/reloc_test_core.c
40
{ "R_AARCH64_ABS16", absolute_data16, UL(SYM16_ABS_VAL) },
arch/arm64/kernel/reloc_test_core.c
41
{ "R_AARCH64_MOVW_SABS_Gn", signed_movw, UL(SYM64_ABS_VAL) },
arch/arm64/kernel/reloc_test_core.c
42
{ "R_AARCH64_MOVW_UABS_Gn", unsigned_movw, UL(SYM64_ABS_VAL) },
arch/arm64/kvm/hyp/pgtable.c
605
vtcr |= FIELD_PREP(VTCR_EL2_T0SZ, (UL(64) - phys_shift));
arch/csky/include/asm/memory.h
11
#define FIXADDR_TOP _AC(0xffffc000, UL)
arch/csky/include/asm/memory.h
12
#define PKMAP_BASE _AC(0xff800000, UL)
arch/csky/include/asm/memory.h
22
#define FIXADDR_TCM _AC(FIXADDR_TOP - (TCM_NR_PAGES * PAGE_SIZE), UL)
arch/hexagon/include/asm/mem-layout.h
19
#define PAGE_OFFSET _AC(0xc0000000, UL)
arch/loongarch/include/asm/kasan.h
14
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/loongarch/include/asm/page.h
14
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
arch/microblaze/include/asm/asm-compat.h
14
# define __ASM_CONST(x) x##UL
arch/mips/include/asm/mach-cavium-octeon/spaces.h
15
#define CAC_BASE _AC(0x8000000000000000, UL)
arch/mips/include/asm/mach-cavium-octeon/spaces.h
16
#define UNCAC_BASE _AC(0x8000000000000000, UL)
arch/mips/include/asm/mach-cavium-octeon/spaces.h
17
#define IO_BASE _AC(0x8000000000000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
28
# define PHYS_OFFSET _AC(0, UL)
arch/mips/include/asm/mach-generic/spaces.h
33
#define CAC_BASE _AC(0x80000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
35
#define IO_BASE _AC(0xa0000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
38
#define UNCAC_BASE _AC(0xa0000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
42
#define MAP_BASE _AC(0xc0000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
49
#define HIGHMEM_START _AC(0x20000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
63
#define IO_BASE _AC(0x9000000000000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
67
#define UNCAC_BASE _AC(0x9000000000000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
71
#define MAP_BASE _AC(0xc000000000000000, UL)
arch/mips/include/asm/mach-generic/spaces.h
80
#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
arch/mips/include/asm/mach-ip22/spaces.h
13
#define PHYS_OFFSET _AC(0x08000000, UL)
arch/mips/include/asm/mach-ip27/spaces.h
21
#define HSPEC_BASE _AC(0x9000000000000000, UL)
arch/mips/include/asm/mach-ip27/spaces.h
22
#define IO_BASE _AC(0x9200000000000000, UL)
arch/mips/include/asm/mach-ip27/spaces.h
23
#define MSPEC_BASE _AC(0x9400000000000000, UL)
arch/mips/include/asm/mach-ip27/spaces.h
24
#define UNCAC_BASE _AC(0x9600000000000000, UL)
arch/mips/include/asm/mach-ip27/spaces.h
25
#define CAC_BASE _AC(0xa800000000000000, UL)
arch/mips/include/asm/mach-ip28/spaces.h
14
#define PHYS_OFFSET _AC(0x20000000, UL)
arch/mips/include/asm/mach-ip30/spaces.h
12
#define PHYS_OFFSET _AC(0x20000000, UL)
arch/mips/include/asm/mach-ip30/spaces.h
15
#define CAC_BASE _AC(0xA800000000000000, UL)
arch/mips/include/asm/mach-loongson2ef/spaces.h
6
#define CAC_BASE _AC(0x9800000000000000, UL)
arch/mips/include/asm/mach-loongson64/spaces.h
10
#define PCI_PORT_BASE _AC(0xc000000000000000 + SZ_128K, UL)
arch/mips/include/asm/mach-loongson64/spaces.h
6
#define CAC_BASE _AC(0x9800000000000000, UL)
arch/mips/include/asm/mach-malta/spaces.h
36
#define PAGE_OFFSET _AC(0x0, UL)
arch/mips/include/asm/mach-malta/spaces.h
37
#define PHYS_OFFSET _AC(0x80000000, UL)
arch/mips/include/asm/mach-malta/spaces.h
38
#define HIGHMEM_START _AC(0xffff0000, UL)
arch/mips/include/asm/mach-pic32/spaces.h
10
#define PHYS_OFFSET _AC(0x08000000, UL)
arch/mips/include/asm/page.h
44
#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
arch/mips/sgi-ip30/ip30-setup.c
33
#define IP30_MAX_PROM_MEMORY _AC(0x40000000, UL)
arch/mips/sgi-ip30/ip30-setup.c
38
#define IP30_MEMORY_BASE _AC(0x20000000, UL)
arch/mips/sgi-ip30/ip30-xtalk.c
25
#define IP30_WIDGET_XBOW _AC(0x0, UL) /* XBow is always 0 */
arch/mips/sgi-ip30/ip30-xtalk.c
26
#define IP30_WIDGET_HEART _AC(0x8, UL) /* HEART is always 8 */
arch/mips/sgi-ip30/ip30-xtalk.c
27
#define IP30_WIDGET_PCI_BASE _AC(0xf, UL) /* BaseIO PCI is always 15 */
arch/powerpc/boot/page.h
11
#define __ASM_CONST(x) x##UL
arch/powerpc/include/asm/asm-const.h
11
# define __ASM_CONST(x) x##UL
arch/powerpc/include/asm/book3s/64/kup.h
10
#define AMR_KUEP_BLOCKED UL(0x5455555555555555)
arch/powerpc/include/asm/book3s/64/kup.h
8
#define AMR_KUAP_BLOCK_READ UL(0x5455555555555555)
arch/powerpc/include/asm/book3s/64/kup.h
9
#define AMR_KUAP_BLOCK_WRITE UL(0xa8aaaaaaaaaaaaaa)
arch/powerpc/include/asm/task_size_32.h
15
#define MODULES_BASE (MODULES_VADDR & ~(UL(SZ_4M) - 1))
arch/powerpc/include/asm/task_size_32.h
20
#define MODULES_END (ASM_CONST(CONFIG_PAGE_OFFSET) & ~(UL(SZ_256M) - 1))
arch/powerpc/include/asm/task_size_32.h
23
#define MODULES_BASE (MODULES_VADDR & ~(UL(SZ_256M) - 1))
arch/powerpc/include/asm/task_size_32.h
28
#define USER_TOP ((ASM_CONST(CONFIG_PAGE_OFFSET) - SZ_128K) & ~(UL(SZ_128K) - 1))
arch/powerpc/include/asm/uaccess.h
517
if (TASK_SIZE <= UL(SZ_2G) && border >= UL(SZ_2G))
arch/riscv/errata/thead/errata.c
25
#define SXSTATUS_MAEE _AC(0x200000, UL)
arch/riscv/include/asm/csr.h
13
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
arch/riscv/include/asm/csr.h
137
#define HSTATUS_HUPMM _AC(0x3000000000000, UL)
arch/riscv/include/asm/csr.h
138
#define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL)
arch/riscv/include/asm/csr.h
139
#define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL)
arch/riscv/include/asm/csr.h
14
#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
arch/riscv/include/asm/csr.h
140
#define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL)
arch/riscv/include/asm/csr.h
141
#define HSTATUS_VSXL _AC(0x300000000, UL)
arch/riscv/include/asm/csr.h
144
#define HSTATUS_VTSR _AC(0x00400000, UL)
arch/riscv/include/asm/csr.h
145
#define HSTATUS_VTW _AC(0x00200000, UL)
arch/riscv/include/asm/csr.h
146
#define HSTATUS_VTVM _AC(0x00100000, UL)
arch/riscv/include/asm/csr.h
147
#define HSTATUS_VGEIN _AC(0x0003f000, UL)
arch/riscv/include/asm/csr.h
149
#define HSTATUS_HU _AC(0x00000200, UL)
arch/riscv/include/asm/csr.h
15
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
arch/riscv/include/asm/csr.h
150
#define HSTATUS_SPVP _AC(0x00000100, UL)
arch/riscv/include/asm/csr.h
151
#define HSTATUS_SPV _AC(0x00000080, UL)
arch/riscv/include/asm/csr.h
152
#define HSTATUS_GVA _AC(0x00000040, UL)
arch/riscv/include/asm/csr.h
153
#define HSTATUS_VSBE _AC(0x00000020, UL)
arch/riscv/include/asm/csr.h
156
#define HGATP_MODE_OFF _AC(0, UL)
arch/riscv/include/asm/csr.h
157
#define HGATP_MODE_SV32X4 _AC(1, UL)
arch/riscv/include/asm/csr.h
158
#define HGATP_MODE_SV39X4 _AC(8, UL)
arch/riscv/include/asm/csr.h
159
#define HGATP_MODE_SV48X4 _AC(9, UL)
arch/riscv/include/asm/csr.h
16
#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
arch/riscv/include/asm/csr.h
160
#define HGATP_MODE_SV57X4 _AC(10, UL)
arch/riscv/include/asm/csr.h
17
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
arch/riscv/include/asm/csr.h
18
#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
arch/riscv/include/asm/csr.h
188
#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \
arch/riscv/include/asm/csr.h
189
(_AC(1, UL) << IRQ_S_TIMER) | \
arch/riscv/include/asm/csr.h
19
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
arch/riscv/include/asm/csr.h
190
(_AC(1, UL) << IRQ_S_EXT) | \
arch/riscv/include/asm/csr.h
191
(_AC(1, UL) << IRQ_PMU_OVF))
arch/riscv/include/asm/csr.h
22
#define SR_SPELP _AC(0x00800000, UL)
arch/riscv/include/asm/csr.h
222
#define ENVCFG_CBZE (_AC(1, UL) << 7)
arch/riscv/include/asm/csr.h
223
#define ENVCFG_CBCFE (_AC(1, UL) << 6)
arch/riscv/include/asm/csr.h
224
#define ENVCFG_LPE (_AC(1, UL) << 2)
arch/riscv/include/asm/csr.h
225
#define ENVCFG_SSE (_AC(1, UL) << 3)
arch/riscv/include/asm/csr.h
227
#define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)
arch/riscv/include/asm/csr.h
228
#define ENVCFG_CBIE_ILL _AC(0x0, UL)
arch/riscv/include/asm/csr.h
229
#define ENVCFG_CBIE_FLUSH _AC(0x1, UL)
arch/riscv/include/asm/csr.h
23
#define SR_MPELP _AC(0x020000000000, UL)
arch/riscv/include/asm/csr.h
230
#define ENVCFG_CBIE_INV _AC(0x3, UL)
arch/riscv/include/asm/csr.h
231
#define ENVCFG_FIOM _AC(0x1, UL)
arch/riscv/include/asm/csr.h
30
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
arch/riscv/include/asm/csr.h
31
#define SR_FS_OFF _AC(0x00000000, UL)
arch/riscv/include/asm/csr.h
32
#define SR_FS_INITIAL _AC(0x00002000, UL)
arch/riscv/include/asm/csr.h
33
#define SR_FS_CLEAN _AC(0x00004000, UL)
arch/riscv/include/asm/csr.h
34
#define SR_FS_DIRTY _AC(0x00006000, UL)
arch/riscv/include/asm/csr.h
36
#define SR_VS _AC(0x00000600, UL) /* Vector Status */
arch/riscv/include/asm/csr.h
37
#define SR_VS_OFF _AC(0x00000000, UL)
arch/riscv/include/asm/csr.h
38
#define SR_VS_INITIAL _AC(0x00000200, UL)
arch/riscv/include/asm/csr.h
39
#define SR_VS_CLEAN _AC(0x00000400, UL)
arch/riscv/include/asm/csr.h
40
#define SR_VS_DIRTY _AC(0x00000600, UL)
arch/riscv/include/asm/csr.h
42
#define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */
arch/riscv/include/asm/csr.h
43
#define SR_VS_OFF_THEAD _AC(0x00000000, UL)
arch/riscv/include/asm/csr.h
44
#define SR_VS_INITIAL_THEAD _AC(0x00800000, UL)
arch/riscv/include/asm/csr.h
45
#define SR_VS_CLEAN_THEAD _AC(0x01000000, UL)
arch/riscv/include/asm/csr.h
46
#define SR_VS_DIRTY_THEAD _AC(0x01800000, UL)
arch/riscv/include/asm/csr.h
461
#define VTYPE_VLMUL _AC(7, UL)
arch/riscv/include/asm/csr.h
462
#define VTYPE_VLMUL_FRAC _AC(4, UL)
arch/riscv/include/asm/csr.h
464
#define VTYPE_VSEW (_AC(7, UL) << VTYPE_VSEW_SHIFT)
arch/riscv/include/asm/csr.h
466
#define VTYPE_VTA (_AC(1, UL) << VTYPE_VTA_SHIFT)
arch/riscv/include/asm/csr.h
468
#define VTYPE_VMA (_AC(1, UL) << VTYPE_VMA_SHIFT)
arch/riscv/include/asm/csr.h
470
#define VTYPE_VILL (_AC(1, UL) << VTYPE_VILL_SHIFT)
arch/riscv/include/asm/csr.h
472
#define VTYPE_VLMUL_THEAD _AC(3, UL)
arch/riscv/include/asm/csr.h
474
#define VTYPE_VSEW_THEAD (_AC(7, UL) << VTYPE_VSEW_THEAD_SHIFT)
arch/riscv/include/asm/csr.h
476
#define VTYPE_VEDIV_THEAD (_AC(3, UL) << VTYPE_VEDIV_THEAD_SHIFT)
arch/riscv/include/asm/csr.h
48
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
arch/riscv/include/asm/csr.h
480
#define SEED_OPST_MASK _AC(0xC0000000, UL)
arch/riscv/include/asm/csr.h
481
#define SEED_OPST_BIST _AC(0x00000000, UL)
arch/riscv/include/asm/csr.h
482
#define SEED_OPST_WAIT _AC(0x40000000, UL)
arch/riscv/include/asm/csr.h
483
#define SEED_OPST_ES16 _AC(0x80000000, UL)
arch/riscv/include/asm/csr.h
484
#define SEED_OPST_DEAD _AC(0xC0000000, UL)
arch/riscv/include/asm/csr.h
485
#define SEED_ENTROPY_MASK _AC(0xFFFF, UL)
arch/riscv/include/asm/csr.h
49
#define SR_XS_OFF _AC(0x00000000, UL)
arch/riscv/include/asm/csr.h
50
#define SR_XS_INITIAL _AC(0x00008000, UL)
arch/riscv/include/asm/csr.h
51
#define SR_XS_CLEAN _AC(0x00010000, UL)
arch/riscv/include/asm/csr.h
52
#define SR_XS_DIRTY _AC(0x00018000, UL)
arch/riscv/include/asm/csr.h
538
# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF)
arch/riscv/include/asm/csr.h
543
#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
arch/riscv/include/asm/csr.h
544
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
arch/riscv/include/asm/csr.h
545
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
arch/riscv/include/asm/csr.h
57
#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
arch/riscv/include/asm/csr.h
59
#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
arch/riscv/include/asm/csr.h
63
#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
arch/riscv/include/asm/csr.h
64
#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
arch/riscv/include/asm/csr.h
65
#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
arch/riscv/include/asm/csr.h
70
#define SATP_PPN _AC(0x003FFFFF, UL)
arch/riscv/include/asm/csr.h
71
#define SATP_MODE_32 _AC(0x80000000, UL)
arch/riscv/include/asm/csr.h
75
#define SATP_ASID_MASK _AC(0x1FF, UL)
arch/riscv/include/asm/csr.h
77
#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
arch/riscv/include/asm/csr.h
78
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
arch/riscv/include/asm/csr.h
79
#define SATP_MODE_48 _AC(0x9000000000000000, UL)
arch/riscv/include/asm/csr.h
80
#define SATP_MODE_57 _AC(0xa000000000000000, UL)
arch/riscv/include/asm/csr.h
84
#define SATP_ASID_MASK _AC(0xFFFF, UL)
arch/riscv/include/asm/csr.h
88
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
arch/riscv/include/asm/kasan.h
28
#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
arch/riscv/include/asm/kasan.h
37
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/riscv/include/asm/page.h
18
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
arch/riscv/include/asm/page.h
29
#define PAGE_OFFSET_L5 _AC(0xff60000000000000, UL)
arch/riscv/include/asm/page.h
30
#define PAGE_OFFSET_L4 _AC(0xffffaf8000000000, UL)
arch/riscv/include/asm/page.h
31
#define PAGE_OFFSET_L3 _AC(0xffffffd600000000, UL)
arch/riscv/include/asm/page.h
38
#define PAGE_OFFSET _AC(0xc0000000, UL)
arch/riscv/include/asm/pgtable-32.h
15
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
arch/riscv/include/asm/pgtable-64.h
22
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
arch/riscv/include/asm/pgtable-64.h
31
#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
arch/riscv/include/asm/pgtable-64.h
36
#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
arch/riscv/include/asm/pgtable-64.h
41
#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
arch/riscv/include/asm/pgtable.h
1250
#define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE)
arch/riscv/include/asm/pgtable.h
1266
#define TASK_SIZE _AC(-1, UL)
arch/riscv/include/asm/pgtable.h
1267
#define VMALLOC_START _AC(0, UL)
arch/riscv/include/asm/pgtable.h
16
#define KERNEL_LINK_ADDR UL(0)
arch/riscv/include/asm/pgtable.h
18
#define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL)
arch/riscv/include/asm/pgtable.h
20
#define KERN_VIRT_SIZE (UL(-1))
arch/riscv/include/asm/pgtable.h
23
#define ADDRESS_SPACE_END (UL(-1))
arch/riscv/include/asm/processor.h
32
#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
arch/riscv/include/asm/processor.h
53
#define TASK_UNMAPPED_BASE PAGE_ALIGN((UL(1) << MMAP_MIN_VA_BITS) / 3)
arch/s390/include/asm/kasan.h
11
(_AC(1, UL) << (_REGION1_SHIFT - KASAN_SHADOW_SCALE_SHIFT))
arch/s390/include/asm/kasan.h
12
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/s390/include/asm/lowcore.h
23
#define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
arch/s390/include/asm/page.h
17
#define PAGE_DEFAULT_ACC _AC(0, UL)
arch/s390/include/asm/ptrace.h
28
#define PSW32_MASK_PER _AC(0x40000000, UL)
arch/s390/include/asm/ptrace.h
29
#define PSW32_MASK_DAT _AC(0x04000000, UL)
arch/s390/include/asm/ptrace.h
30
#define PSW32_MASK_IO _AC(0x02000000, UL)
arch/s390/include/asm/ptrace.h
31
#define PSW32_MASK_EXT _AC(0x01000000, UL)
arch/s390/include/asm/ptrace.h
32
#define PSW32_MASK_KEY _AC(0x00F00000, UL)
arch/s390/include/asm/ptrace.h
33
#define PSW32_MASK_BASE _AC(0x00080000, UL) /* Always one */
arch/s390/include/asm/ptrace.h
34
#define PSW32_MASK_MCHECK _AC(0x00040000, UL)
arch/s390/include/asm/ptrace.h
35
#define PSW32_MASK_WAIT _AC(0x00020000, UL)
arch/s390/include/asm/ptrace.h
36
#define PSW32_MASK_PSTATE _AC(0x00010000, UL)
arch/s390/include/asm/ptrace.h
37
#define PSW32_MASK_ASC _AC(0x0000C000, UL)
arch/s390/include/asm/ptrace.h
38
#define PSW32_MASK_CC _AC(0x00003000, UL)
arch/s390/include/asm/ptrace.h
39
#define PSW32_MASK_PM _AC(0x00000f00, UL)
arch/s390/include/asm/ptrace.h
40
#define PSW32_MASK_RI _AC(0x00000080, UL)
arch/s390/include/asm/ptrace.h
42
#define PSW32_ADDR_AMODE _AC(0x80000000, UL)
arch/s390/include/asm/ptrace.h
43
#define PSW32_ADDR_INSN _AC(0x7FFFFFFF, UL)
arch/s390/include/asm/ptrace.h
47
#define PSW32_ASC_PRIMARY _AC(0x00000000, UL)
arch/s390/include/asm/ptrace.h
48
#define PSW32_ASC_ACCREG _AC(0x00004000, UL)
arch/s390/include/asm/ptrace.h
49
#define PSW32_ASC_SECONDARY _AC(0x00008000, UL)
arch/s390/include/asm/ptrace.h
50
#define PSW32_ASC_HOME _AC(0x0000C000, UL)
arch/s390/include/asm/setup.h
18
#define LPP_PID_MASK _AC(0xffffffff, UL)
arch/s390/include/uapi/asm/ptrace.h
100
#define PSW_ADDR_INSN _AC(0xFFFFFFFFFFFFFFFF, UL)
arch/s390/include/uapi/asm/ptrace.h
102
#define PSW_ASC_PRIMARY _AC(0x0000000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
103
#define PSW_ASC_ACCREG _AC(0x0000400000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
104
#define PSW_ASC_SECONDARY _AC(0x0000800000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
105
#define PSW_ASC_HOME _AC(0x0000C00000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
81
#define PSW_MASK_PER _AC(0x4000000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
82
#define PSW_MASK_DAT _AC(0x0400000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
83
#define PSW_MASK_IO _AC(0x0200000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
84
#define PSW_MASK_EXT _AC(0x0100000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
85
#define PSW_MASK_BASE _AC(0x0000000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
86
#define PSW_MASK_KEY _AC(0x00F0000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
87
#define PSW_MASK_MCHECK _AC(0x0004000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
88
#define PSW_MASK_WAIT _AC(0x0002000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
89
#define PSW_MASK_PSTATE _AC(0x0001000000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
90
#define PSW_MASK_ASC _AC(0x0000C00000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
91
#define PSW_MASK_CC _AC(0x0000300000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
92
#define PSW_MASK_PM _AC(0x00000F0000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
93
#define PSW_MASK_RI _AC(0x0000008000000000, UL)
arch/s390/include/uapi/asm/ptrace.h
94
#define PSW_MASK_EA _AC(0x0000000100000000, UL)
arch/s390/include/uapi/asm/ptrace.h
95
#define PSW_MASK_BA _AC(0x0000000080000000, UL)
arch/s390/include/uapi/asm/ptrace.h
97
#define PSW_MASK_USER _AC(0x0000FF0180000000, UL)
arch/s390/include/uapi/asm/ptrace.h
99
#define PSW_ADDR_AMODE _AC(0x0000000000000000, UL)
arch/sparc/include/asm/dcu.h
10
#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
arch/sparc/include/asm/dcu.h
11
#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
arch/sparc/include/asm/dcu.h
12
#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
arch/sparc/include/asm/dcu.h
13
#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
arch/sparc/include/asm/dcu.h
14
#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
arch/sparc/include/asm/dcu.h
15
#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
arch/sparc/include/asm/dcu.h
16
#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
arch/sparc/include/asm/dcu.h
17
#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
arch/sparc/include/asm/dcu.h
18
#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
arch/sparc/include/asm/dcu.h
19
#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
arch/sparc/include/asm/dcu.h
20
#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
arch/sparc/include/asm/dcu.h
21
#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
arch/sparc/include/asm/dcu.h
22
#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
arch/sparc/include/asm/dcu.h
23
#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
arch/sparc/include/asm/dcu.h
24
#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
arch/sparc/include/asm/dcu.h
25
#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
arch/sparc/include/asm/dcu.h
26
#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
arch/sparc/include/asm/dcu.h
8
#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
arch/sparc/include/asm/dcu.h
9
#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
arch/sparc/include/asm/lsu.h
10
#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
arch/sparc/include/asm/lsu.h
11
#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
arch/sparc/include/asm/lsu.h
12
#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
arch/sparc/include/asm/lsu.h
13
#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
arch/sparc/include/asm/lsu.h
14
#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
arch/sparc/include/asm/lsu.h
15
#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
arch/sparc/include/asm/lsu.h
16
#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
arch/sparc/include/asm/lsu.h
17
#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
arch/sparc/include/asm/lsu.h
18
#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
arch/sparc/include/asm/lsu.h
8
#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
arch/sparc/include/asm/lsu.h
9
#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
arch/sparc/include/asm/mmu_64.h
11
#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
arch/sparc/include/asm/mmu_64.h
22
#define CTX_PGSZ_8KB _AC(0x0,UL)
arch/sparc/include/asm/mmu_64.h
23
#define CTX_PGSZ_64KB _AC(0x1,UL)
arch/sparc/include/asm/mmu_64.h
24
#define CTX_PGSZ_512KB _AC(0x2,UL)
arch/sparc/include/asm/mmu_64.h
25
#define CTX_PGSZ_4MB _AC(0x3,UL)
arch/sparc/include/asm/mmu_64.h
26
#define CTX_PGSZ_BITS _AC(0x7,UL)
arch/sparc/include/asm/page_64.h
125
_AC(0x0000000070000000,UL) : \
arch/sparc/include/asm/page_64.h
22
#define REAL_HPAGE_SIZE (_AC(1,UL) << REAL_HPAGE_SHIFT)
arch/sparc/include/asm/page_64.h
25
#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
arch/sparc/include/asm/page_64.h
29
#define REAL_HPAGE_PER_HPAGE (_AC(1,UL) << (HPAGE_SHIFT - REAL_HPAGE_SHIFT))
arch/sparc/include/asm/pgtable_32.h
424
#define VMALLOC_START _AC(0xfe600000,UL)
arch/sparc/include/asm/pgtable_32.h
425
#define VMALLOC_END _AC(0xffc00000,UL)
arch/sparc/include/asm/pgtable_64.h
112
#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
arch/sparc/include/asm/pgtable_64.h
113
#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
arch/sparc/include/asm/pgtable_64.h
114
#define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
arch/sparc/include/asm/pgtable_64.h
115
#define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */
arch/sparc/include/asm/pgtable_64.h
119
#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
arch/sparc/include/asm/pgtable_64.h
120
#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
arch/sparc/include/asm/pgtable_64.h
121
#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
arch/sparc/include/asm/pgtable_64.h
122
#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
arch/sparc/include/asm/pgtable_64.h
123
#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
arch/sparc/include/asm/pgtable_64.h
124
#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
arch/sparc/include/asm/pgtable_64.h
125
#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
arch/sparc/include/asm/pgtable_64.h
126
#define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
arch/sparc/include/asm/pgtable_64.h
127
#define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */
arch/sparc/include/asm/pgtable_64.h
128
#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
arch/sparc/include/asm/pgtable_64.h
129
#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
arch/sparc/include/asm/pgtable_64.h
130
#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
arch/sparc/include/asm/pgtable_64.h
131
#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
arch/sparc/include/asm/pgtable_64.h
132
#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
arch/sparc/include/asm/pgtable_64.h
133
#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
arch/sparc/include/asm/pgtable_64.h
134
#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
arch/sparc/include/asm/pgtable_64.h
135
#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
arch/sparc/include/asm/pgtable_64.h
136
#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
arch/sparc/include/asm/pgtable_64.h
137
#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
arch/sparc/include/asm/pgtable_64.h
138
#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
arch/sparc/include/asm/pgtable_64.h
139
#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
arch/sparc/include/asm/pgtable_64.h
140
#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
arch/sparc/include/asm/pgtable_64.h
141
#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
arch/sparc/include/asm/pgtable_64.h
142
#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
arch/sparc/include/asm/pgtable_64.h
143
#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
arch/sparc/include/asm/pgtable_64.h
144
#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
arch/sparc/include/asm/pgtable_64.h
145
#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
arch/sparc/include/asm/pgtable_64.h
146
#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
arch/sparc/include/asm/pgtable_64.h
147
#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
arch/sparc/include/asm/pgtable_64.h
150
#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
arch/sparc/include/asm/pgtable_64.h
151
#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
arch/sparc/include/asm/pgtable_64.h
152
#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
arch/sparc/include/asm/pgtable_64.h
153
#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
arch/sparc/include/asm/pgtable_64.h
154
#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
arch/sparc/include/asm/pgtable_64.h
155
#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
arch/sparc/include/asm/pgtable_64.h
156
#define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
arch/sparc/include/asm/pgtable_64.h
157
#define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */
arch/sparc/include/asm/pgtable_64.h
158
#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
arch/sparc/include/asm/pgtable_64.h
159
#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
arch/sparc/include/asm/pgtable_64.h
160
#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
arch/sparc/include/asm/pgtable_64.h
161
#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
arch/sparc/include/asm/pgtable_64.h
162
#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
arch/sparc/include/asm/pgtable_64.h
164
#define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */
arch/sparc/include/asm/pgtable_64.h
165
#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
arch/sparc/include/asm/pgtable_64.h
166
#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
arch/sparc/include/asm/pgtable_64.h
167
#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
arch/sparc/include/asm/pgtable_64.h
168
#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
arch/sparc/include/asm/pgtable_64.h
169
#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
arch/sparc/include/asm/pgtable_64.h
170
#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
arch/sparc/include/asm/pgtable_64.h
171
#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
arch/sparc/include/asm/pgtable_64.h
172
#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
arch/sparc/include/asm/pgtable_64.h
173
#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
arch/sparc/include/asm/pgtable_64.h
174
#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
arch/sparc/include/asm/pgtable_64.h
175
#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
arch/sparc/include/asm/pgtable_64.h
176
#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
arch/sparc/include/asm/pgtable_64.h
177
#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
arch/sparc/include/asm/pgtable_64.h
178
#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
arch/sparc/include/asm/pgtable_64.h
179
#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
arch/sparc/include/asm/pgtable_64.h
192
#define _PAGE_SWP_EXCLUSIVE _AC(0x0000000000100000, UL)
arch/sparc/include/asm/pgtable_64.h
37
#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
arch/sparc/include/asm/pgtable_64.h
38
#define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
arch/sparc/include/asm/pgtable_64.h
39
#define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
arch/sparc/include/asm/pgtable_64.h
40
#define MODULES_VADDR _AC(0x0000000010000000,UL)
arch/sparc/include/asm/pgtable_64.h
41
#define MODULES_LEN _AC(0x00000000e0000000,UL)
arch/sparc/include/asm/pgtable_64.h
42
#define MODULES_END _AC(0x00000000f0000000,UL)
arch/sparc/include/asm/pgtable_64.h
43
#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
arch/sparc/include/asm/pgtable_64.h
44
#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
arch/sparc/include/asm/pgtable_64.h
45
#define VMALLOC_START _AC(0x0000000100000000,UL)
arch/sparc/include/asm/pgtable_64.h
52
#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
arch/sparc/include/asm/pgtable_64.h
60
#define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
arch/sparc/include/asm/pgtable_64.h
66
#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
arch/sparc/include/asm/sfafsr.h
11
#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
arch/sparc/include/asm/sfafsr.h
13
#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
arch/sparc/include/asm/sfafsr.h
15
#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
arch/sparc/include/asm/sfafsr.h
17
#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
arch/sparc/include/asm/sfafsr.h
19
#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
arch/sparc/include/asm/sfafsr.h
21
#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
arch/sparc/include/asm/sfafsr.h
23
#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
arch/sparc/include/asm/sfafsr.h
25
#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
arch/sparc/include/asm/sfafsr.h
27
#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
arch/sparc/include/asm/sfafsr.h
29
#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
arch/sparc/include/asm/sfafsr.h
31
#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
arch/sparc/include/asm/sfafsr.h
33
#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
arch/sparc/include/asm/sfafsr.h
35
#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
arch/sparc/include/asm/sfafsr.h
37
#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
arch/sparc/include/asm/sfafsr.h
44
#define UDBE_UE (_AC(1,UL) << 9)
arch/sparc/include/asm/sfafsr.h
45
#define UDBE_CE (_AC(1,UL) << 8)
arch/sparc/include/asm/sfafsr.h
46
#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
arch/sparc/include/asm/sfafsr.h
59
#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
arch/sparc/include/asm/sfafsr.h
61
#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
arch/sparc/include/asm/sfafsr.h
63
#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
arch/sparc/include/asm/sfafsr.h
65
#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
arch/sparc/include/asm/sfafsr.h
67
#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
arch/sparc/include/asm/sfafsr.h
9
#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
arch/sparc/include/uapi/asm/pstate.h
100
#define VERS_MAXWIN _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
arch/sparc/include/uapi/asm/pstate.h
103
#define CFR_AES _AC(0x0000000000000001,UL) /* Supports AES opcodes */
arch/sparc/include/uapi/asm/pstate.h
104
#define CFR_DES _AC(0x0000000000000002,UL) /* Supports DES opcodes */
arch/sparc/include/uapi/asm/pstate.h
105
#define CFR_KASUMI _AC(0x0000000000000004,UL) /* Supports KASUMI opcodes */
arch/sparc/include/uapi/asm/pstate.h
106
#define CFR_CAMELLIA _AC(0x0000000000000008,UL) /* Supports CAMELLIA opcodes*/
arch/sparc/include/uapi/asm/pstate.h
107
#define CFR_MD5 _AC(0x0000000000000010,UL) /* Supports MD5 opcodes */
arch/sparc/include/uapi/asm/pstate.h
108
#define CFR_SHA1 _AC(0x0000000000000020,UL) /* Supports SHA1 opcodes */
arch/sparc/include/uapi/asm/pstate.h
109
#define CFR_SHA256 _AC(0x0000000000000040,UL) /* Supports SHA256 opcodes */
arch/sparc/include/uapi/asm/pstate.h
110
#define CFR_SHA512 _AC(0x0000000000000080,UL) /* Supports SHA512 opcodes */
arch/sparc/include/uapi/asm/pstate.h
111
#define CFR_MPMUL _AC(0x0000000000000100,UL) /* Supports MPMUL opcodes */
arch/sparc/include/uapi/asm/pstate.h
112
#define CFR_MONTMUL _AC(0x0000000000000200,UL) /* Supports MONTMUL opcodes */
arch/sparc/include/uapi/asm/pstate.h
113
#define CFR_MONTSQR _AC(0x0000000000000400,UL) /* Supports MONTSQR opcodes */
arch/sparc/include/uapi/asm/pstate.h
114
#define CFR_CRC32C _AC(0x0000000000000800,UL) /* Supports CRC32C opcodes */
arch/sparc/include/uapi/asm/pstate.h
18
#define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
arch/sparc/include/uapi/asm/pstate.h
19
#define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */
arch/sparc/include/uapi/asm/pstate.h
20
#define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
arch/sparc/include/uapi/asm/pstate.h
21
#define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
arch/sparc/include/uapi/asm/pstate.h
22
#define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
arch/sparc/include/uapi/asm/pstate.h
23
#define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
arch/sparc/include/uapi/asm/pstate.h
24
#define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
arch/sparc/include/uapi/asm/pstate.h
25
#define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
arch/sparc/include/uapi/asm/pstate.h
26
#define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
arch/sparc/include/uapi/asm/pstate.h
27
#define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
arch/sparc/include/uapi/asm/pstate.h
28
#define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
arch/sparc/include/uapi/asm/pstate.h
29
#define PSTATE_AM _AC(0x0000000000000008,UL) /* Address Mask. */
arch/sparc/include/uapi/asm/pstate.h
30
#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */
arch/sparc/include/uapi/asm/pstate.h
31
#define PSTATE_IE _AC(0x0000000000000002,UL) /* Interrupt Enable. */
arch/sparc/include/uapi/asm/pstate.h
32
#define PSTATE_AG _AC(0x0000000000000001,UL) /* Alternate Globals. */
arch/sparc/include/uapi/asm/pstate.h
41
#define TSTATE_GL _AC(0x0000070000000000,UL) /* Global reg level */
arch/sparc/include/uapi/asm/pstate.h
42
#define TSTATE_CCR _AC(0x000000ff00000000,UL) /* Condition Codes. */
arch/sparc/include/uapi/asm/pstate.h
43
#define TSTATE_XCC _AC(0x000000f000000000,UL) /* Condition Codes. */
arch/sparc/include/uapi/asm/pstate.h
44
#define TSTATE_XNEG _AC(0x0000008000000000,UL) /* %xcc Negative. */
arch/sparc/include/uapi/asm/pstate.h
45
#define TSTATE_XZERO _AC(0x0000004000000000,UL) /* %xcc Zero. */
arch/sparc/include/uapi/asm/pstate.h
46
#define TSTATE_XOVFL _AC(0x0000002000000000,UL) /* %xcc Overflow. */
arch/sparc/include/uapi/asm/pstate.h
47
#define TSTATE_XCARRY _AC(0x0000001000000000,UL) /* %xcc Carry. */
arch/sparc/include/uapi/asm/pstate.h
48
#define TSTATE_ICC _AC(0x0000000f00000000,UL) /* Condition Codes. */
arch/sparc/include/uapi/asm/pstate.h
49
#define TSTATE_INEG _AC(0x0000000800000000,UL) /* %icc Negative. */
arch/sparc/include/uapi/asm/pstate.h
50
#define TSTATE_IZERO _AC(0x0000000400000000,UL) /* %icc Zero. */
arch/sparc/include/uapi/asm/pstate.h
51
#define TSTATE_IOVFL _AC(0x0000000200000000,UL) /* %icc Overflow. */
arch/sparc/include/uapi/asm/pstate.h
52
#define TSTATE_ICARRY _AC(0x0000000100000000,UL) /* %icc Carry. */
arch/sparc/include/uapi/asm/pstate.h
53
#define TSTATE_ASI _AC(0x00000000ff000000,UL) /* AddrSpace ID. */
arch/sparc/include/uapi/asm/pstate.h
54
#define TSTATE_PIL _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
arch/sparc/include/uapi/asm/pstate.h
55
#define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */
arch/sparc/include/uapi/asm/pstate.h
60
#define TSTATE_IG _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
arch/sparc/include/uapi/asm/pstate.h
61
#define TSTATE_MCDE _AC(0x0000000000080000,UL) /* MCD enable. */
arch/sparc/include/uapi/asm/pstate.h
62
#define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
arch/sparc/include/uapi/asm/pstate.h
63
#define TSTATE_CLE _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
arch/sparc/include/uapi/asm/pstate.h
64
#define TSTATE_TLE _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
arch/sparc/include/uapi/asm/pstate.h
65
#define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */
arch/sparc/include/uapi/asm/pstate.h
66
#define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */
arch/sparc/include/uapi/asm/pstate.h
67
#define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */
arch/sparc/include/uapi/asm/pstate.h
68
#define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */
arch/sparc/include/uapi/asm/pstate.h
69
#define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
arch/sparc/include/uapi/asm/pstate.h
70
#define TSTATE_PEF _AC(0x0000000000001000,UL) /* FPU Enable. */
arch/sparc/include/uapi/asm/pstate.h
71
#define TSTATE_AM _AC(0x0000000000000800,UL) /* Address Mask. */
arch/sparc/include/uapi/asm/pstate.h
72
#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
arch/sparc/include/uapi/asm/pstate.h
73
#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
arch/sparc/include/uapi/asm/pstate.h
74
#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
arch/sparc/include/uapi/asm/pstate.h
75
#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
arch/sparc/include/uapi/asm/pstate.h
76
#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
arch/sparc/include/uapi/asm/pstate.h
85
#define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */
arch/sparc/include/uapi/asm/pstate.h
86
#define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */
arch/sparc/include/uapi/asm/pstate.h
87
#define FPRS_DL _AC(0x0000000000000001,UL) /* Dirty Lower. */
arch/sparc/include/uapi/asm/pstate.h
96
#define VERS_MANUF _AC(0xffff000000000000,UL) /* Manufacturer. */
arch/sparc/include/uapi/asm/pstate.h
97
#define VERS_IMPL _AC(0x0000ffff00000000,UL) /* Implementation. */
arch/sparc/include/uapi/asm/pstate.h
98
#define VERS_MASK _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
arch/sparc/include/uapi/asm/pstate.h
99
#define VERS_MAXTL _AC(0x000000000000ff00,UL) /* Max Trap Level. */
arch/um/include/asm/kasan.h
8
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/x86/include/asm/boot.h
15
#define MIN_KERNEL_ALIGN (_AC(1, UL) << MIN_KERNEL_ALIGN_LG2)
arch/x86/include/asm/kasan.h
6
#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
arch/x86/include/asm/page_32_types.h
17
#define __PAGE_OFFSET_BASE _AC(CONFIG_PAGE_OFFSET, UL)
arch/x86/include/asm/page_64_types.h
41
#define __PAGE_OFFSET_BASE_L5 _AC(0xff11000000000000, UL)
arch/x86/include/asm/page_64_types.h
42
#define __PAGE_OFFSET_BASE_L4 _AC(0xffff888000000000, UL)
arch/x86/include/asm/page_64_types.h
46
#define __START_KERNEL_map _AC(0xffffffff80000000, UL)
arch/x86/include/asm/page_types.h
21
#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
arch/x86/include/asm/pgtable_64_types.h
174
# define MODULES_END _AC(0xffffffffff000000, UL)
arch/x86/include/asm/pgtable_64_types.h
176
# define MODULES_END _AC(0xfffffffffe000000, UL)
arch/x86/include/asm/pgtable_64_types.h
180
#define ESPFIX_PGD_ENTRY _AC(-2, UL)
arch/x86/include/asm/pgtable_64_types.h
183
#define CPU_ENTRY_AREA_PGD _AC(-4, UL)
arch/x86/include/asm/pgtable_64_types.h
186
#define EFI_VA_START ( -4 * (_AC(1, UL) << 30))
arch/x86/include/asm/pgtable_64_types.h
187
#define EFI_VA_END (-68 * (_AC(1, UL) << 30))
arch/x86/include/asm/pgtable_64_types.h
59
#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
arch/x86/include/asm/pgtable_64_types.h
82
#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
arch/x86/include/asm/pgtable_64_types.h
84
#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
arch/x86/include/asm/pgtable_64_types.h
86
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
arch/x86/include/uapi/asm/processor-flags.h
154
#define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */
arch/x86/include/uapi/asm/processor-flags.h
32
#define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT)
arch/x86/include/uapi/asm/processor-flags.h
83
#define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))
arch/x86/kernel/kprobes/core.c
65
(((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
arch/x86/kernel/kprobes/core.c
66
(b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
arch/x86/kernel/kprobes/core.c
67
(b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
arch/x86/kernel/kprobes/core.c
68
(bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
arch/x86/kernel/uprobes.c
50
(((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
arch/x86/kernel/uprobes.c
51
(b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
arch/x86/kernel/uprobes.c
52
(b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
arch/x86/kernel/uprobes.c
53
(bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
arch/xtensa/include/asm/page.h
29
#define PAGE_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
arch/xtensa/include/asm/page.h
30
#define PHYS_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
arch/xtensa/include/uapi/asm/types.h
22
# define ___XTENSA_UL_CONST(x) x##UL
drivers/clk/at91/sam9x60.c
39
.acr = UL(0x00020010),
drivers/clk/at91/sam9x60.c
52
.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
drivers/clk/at91/sam9x7.c
110
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
drivers/clk/at91/sam9x7.c
119
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
drivers/clk/at91/sam9x7.c
127
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
drivers/clk/at91/sam9x7.c
135
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
drivers/clk/at91/sam9x7.c
143
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
drivers/clk/at91/sama7d65.c
141
.acr = UL(0x00070010),
drivers/clk/at91/sama7d65.c
150
.acr = UL(0x00070010),
drivers/clk/at91/sama7d65.c
158
.acr = UL(0x00070010),
drivers/clk/at91/sama7d65.c
166
.acr = UL(0x12020010),
drivers/clk/at91/sama7g5.c
116
.acr = UL(0x00070010),
drivers/clk/at91/sama7g5.c
125
.acr = UL(0x00070010),
drivers/infiniband/sw/siw/siw_mem.h
46
#define PAGES_PER_CHUNK (_AC(1, UL) << CHUNK_SHIFT)
drivers/misc/lkdtm/bugs.c
33
#define REC_STACK_SIZE (_AC(CONFIG_FRAME_WARN, UL) / 2)
drivers/net/ethernet/amazon/ena/ena_netdev.h
42
#define ENA_PAGE_SIZE (_AC(SZ_16K, UL))
fs/ceph/crypto.h
14
#define CEPH_FSCRYPT_BLOCK_SIZE (_AC(1, UL) << CEPH_FSCRYPT_BLOCK_SHIFT)
include/linux/bits.h
8
#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
include/linux/irqchip/arm-gic-v5.h
23
#define GICV5_HWIRQ_TYPE_PPI UL(0x1)
include/linux/irqchip/arm-gic-v5.h
24
#define GICV5_HWIRQ_TYPE_LPI UL(0x2)
include/linux/irqchip/arm-gic-v5.h
25
#define GICV5_HWIRQ_TYPE_SPI UL(0x3)
include/linux/poison.h
13
# define POISON_POINTER_DELTA _AC(CONFIG_ILLEGAL_POINTER_VALUE, UL)
include/uapi/linux/const.h
25
#define _UL(x) (_AC(x, UL))
include/vdso/bits.h
7
#define BIT(nr) (UL(1) << (nr))
include/vdso/page.h
15
#define PAGE_SIZE (_AC(1,UL) << CONFIG_PAGE_SHIFT)
include/xen/interface/xen.h
737
#define __mk_unsigned_long(x) x ## UL
include/xen/page.h
9
#define XEN_PAGE_SIZE (_AC(1, UL) << XEN_PAGE_SHIFT)
mm/zsmalloc.c
92
#define OBJ_INDEX_MASK ((_AC(1, UL) << OBJ_INDEX_BITS) - 1)
mm/zsmalloc.c
99
#define ZS_MAX_PAGES_PER_ZSPAGE (_AC(CONFIG_ZSMALLOC_CHAIN_SIZE, UL))
tools/arch/arm64/include/asm/cputype.h
12
#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
tools/arch/arm64/include/asm/esr.h
101
#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
tools/arch/arm64/include/asm/esr.h
103
#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
tools/arch/arm64/include/asm/esr.h
105
#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
tools/arch/arm64/include/asm/esr.h
107
#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
tools/arch/arm64/include/asm/esr.h
12
#define ESR_ELx_EC_UNKNOWN UL(0x00)
tools/arch/arm64/include/asm/esr.h
13
#define ESR_ELx_EC_WFx UL(0x01)
tools/arch/arm64/include/asm/esr.h
133
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
tools/arch/arm64/include/asm/esr.h
135
#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
tools/arch/arm64/include/asm/esr.h
137
#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
tools/arch/arm64/include/asm/esr.h
139
#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
tools/arch/arm64/include/asm/esr.h
141
#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
tools/arch/arm64/include/asm/esr.h
143
#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
tools/arch/arm64/include/asm/esr.h
145
#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT)
tools/arch/arm64/include/asm/esr.h
147
#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
tools/arch/arm64/include/asm/esr.h
15
#define ESR_ELx_EC_CP15_32 UL(0x03)
tools/arch/arm64/include/asm/esr.h
151
#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
tools/arch/arm64/include/asm/esr.h
153
#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
tools/arch/arm64/include/asm/esr.h
155
#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
tools/arch/arm64/include/asm/esr.h
157
#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
tools/arch/arm64/include/asm/esr.h
159
#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
tools/arch/arm64/include/asm/esr.h
16
#define ESR_ELx_EC_CP15_64 UL(0x04)
tools/arch/arm64/include/asm/esr.h
166
#define ESR_ELx_CV (UL(1) << 24)
tools/arch/arm64/include/asm/esr.h
168
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
tools/arch/arm64/include/asm/esr.h
169
#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
tools/arch/arm64/include/asm/esr.h
17
#define ESR_ELx_EC_CP14_MR UL(0x05)
tools/arch/arm64/include/asm/esr.h
170
#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
tools/arch/arm64/include/asm/esr.h
171
#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
tools/arch/arm64/include/asm/esr.h
172
#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
tools/arch/arm64/include/asm/esr.h
173
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
tools/arch/arm64/include/asm/esr.h
174
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
tools/arch/arm64/include/asm/esr.h
175
#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
tools/arch/arm64/include/asm/esr.h
177
#define DISR_EL1_IDS (UL(1) << 24)
tools/arch/arm64/include/asm/esr.h
18
#define ESR_ELx_EC_CP14_LS UL(0x06)
tools/arch/arm64/include/asm/esr.h
19
#define ESR_ELx_EC_FP_ASIMD UL(0x07)
tools/arch/arm64/include/asm/esr.h
195
#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
tools/arch/arm64/include/asm/esr.h
20
#define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
tools/arch/arm64/include/asm/esr.h
201
#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
tools/arch/arm64/include/asm/esr.h
203
#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
tools/arch/arm64/include/asm/esr.h
205
#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
tools/arch/arm64/include/asm/esr.h
207
#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
tools/arch/arm64/include/asm/esr.h
209
#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
tools/arch/arm64/include/asm/esr.h
21
#define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
tools/arch/arm64/include/asm/esr.h
211
#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
tools/arch/arm64/include/asm/esr.h
23
#define ESR_ELx_EC_CP14_64 UL(0x0C)
tools/arch/arm64/include/asm/esr.h
24
#define ESR_ELx_EC_BTI UL(0x0D)
tools/arch/arm64/include/asm/esr.h
25
#define ESR_ELx_EC_ILL UL(0x0E)
tools/arch/arm64/include/asm/esr.h
27
#define ESR_ELx_EC_SVC32 UL(0x11)
tools/arch/arm64/include/asm/esr.h
28
#define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
tools/arch/arm64/include/asm/esr.h
29
#define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
tools/arch/arm64/include/asm/esr.h
308
#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
tools/arch/arm64/include/asm/esr.h
31
#define ESR_ELx_EC_SVC64 UL(0x15)
tools/arch/arm64/include/asm/esr.h
318
#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
tools/arch/arm64/include/asm/esr.h
32
#define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
tools/arch/arm64/include/asm/esr.h
320
#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
tools/arch/arm64/include/asm/esr.h
322
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
tools/arch/arm64/include/asm/esr.h
324
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
tools/arch/arm64/include/asm/esr.h
326
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
tools/arch/arm64/include/asm/esr.h
33
#define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
tools/arch/arm64/include/asm/esr.h
34
#define ESR_ELx_EC_SYS64 UL(0x18)
tools/arch/arm64/include/asm/esr.h
344
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
tools/arch/arm64/include/asm/esr.h
347
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
tools/arch/arm64/include/asm/esr.h
35
#define ESR_ELx_EC_SVE UL(0x19)
tools/arch/arm64/include/asm/esr.h
350
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
tools/arch/arm64/include/asm/esr.h
352
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
tools/arch/arm64/include/asm/esr.h
36
#define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
tools/arch/arm64/include/asm/esr.h
38
#define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
tools/arch/arm64/include/asm/esr.h
382
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
tools/arch/arm64/include/asm/esr.h
383
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
tools/arch/arm64/include/asm/esr.h
384
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
tools/arch/arm64/include/asm/esr.h
385
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
tools/arch/arm64/include/asm/esr.h
386
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
tools/arch/arm64/include/asm/esr.h
387
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
tools/arch/arm64/include/asm/esr.h
388
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
tools/arch/arm64/include/asm/esr.h
39
#define ESR_ELx_EC_SME UL(0x1D)
tools/arch/arm64/include/asm/esr.h
41
#define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
tools/arch/arm64/include/asm/esr.h
42
#define ESR_ELx_EC_IABT_LOW UL(0x20)
tools/arch/arm64/include/asm/esr.h
43
#define ESR_ELx_EC_IABT_CUR UL(0x21)
tools/arch/arm64/include/asm/esr.h
44
#define ESR_ELx_EC_PC_ALIGN UL(0x22)
tools/arch/arm64/include/asm/esr.h
46
#define ESR_ELx_EC_DABT_LOW UL(0x24)
tools/arch/arm64/include/asm/esr.h
47
#define ESR_ELx_EC_DABT_CUR UL(0x25)
tools/arch/arm64/include/asm/esr.h
48
#define ESR_ELx_EC_SP_ALIGN UL(0x26)
tools/arch/arm64/include/asm/esr.h
49
#define ESR_ELx_EC_MOPS UL(0x27)
tools/arch/arm64/include/asm/esr.h
50
#define ESR_ELx_EC_FP_EXC32 UL(0x28)
tools/arch/arm64/include/asm/esr.h
52
#define ESR_ELx_EC_FP_EXC64 UL(0x2C)
tools/arch/arm64/include/asm/esr.h
54
#define ESR_ELx_EC_SERROR UL(0x2F)
tools/arch/arm64/include/asm/esr.h
55
#define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
tools/arch/arm64/include/asm/esr.h
56
#define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
tools/arch/arm64/include/asm/esr.h
57
#define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
tools/arch/arm64/include/asm/esr.h
58
#define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
tools/arch/arm64/include/asm/esr.h
59
#define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
tools/arch/arm64/include/asm/esr.h
60
#define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
tools/arch/arm64/include/asm/esr.h
62
#define ESR_ELx_EC_BKPT32 UL(0x38)
tools/arch/arm64/include/asm/esr.h
64
#define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
tools/arch/arm64/include/asm/esr.h
66
#define ESR_ELx_EC_BRK64 UL(0x3C)
tools/arch/arm64/include/asm/esr.h
68
#define ESR_ELx_EC_MAX UL(0x3F)
tools/arch/arm64/include/asm/esr.h
72
#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
tools/arch/arm64/include/asm/esr.h
76
#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
tools/arch/arm64/include/asm/esr.h
85
#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
tools/arch/arm64/include/asm/esr.h
89
#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
tools/arch/arm64/include/asm/esr.h
91
#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/esr.h
93
#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/esr.h
94
#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/esr.h
95
#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/esr.h
96
#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/esr.h
97
#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
tools/arch/arm64/include/asm/sysreg.h
1019
#define PIE_NONE_O UL(0x0)
tools/arch/arm64/include/asm/sysreg.h
1020
#define PIE_R_O UL(0x1)
tools/arch/arm64/include/asm/sysreg.h
1021
#define PIE_X_O UL(0x2)
tools/arch/arm64/include/asm/sysreg.h
1022
#define PIE_RX_O UL(0x3)
tools/arch/arm64/include/asm/sysreg.h
1023
#define PIE_RW_O UL(0x5)
tools/arch/arm64/include/asm/sysreg.h
1024
#define PIE_RWnX_O UL(0x6)
tools/arch/arm64/include/asm/sysreg.h
1025
#define PIE_RWX_O UL(0x7)
tools/arch/arm64/include/asm/sysreg.h
1026
#define PIE_R UL(0x8)
tools/arch/arm64/include/asm/sysreg.h
1027
#define PIE_GCS UL(0x9)
tools/arch/arm64/include/asm/sysreg.h
1028
#define PIE_RX UL(0xa)
tools/arch/arm64/include/asm/sysreg.h
1029
#define PIE_RW UL(0xc)
tools/arch/arm64/include/asm/sysreg.h
1030
#define PIE_RWX UL(0xe)
tools/arch/arm64/include/asm/sysreg.h
1031
#define PIE_MASK UL(0xf)
tools/arch/arm64/include/asm/sysreg.h
1040
#define POE_NONE UL(0x0)
tools/arch/arm64/include/asm/sysreg.h
1041
#define POE_R UL(0x1)
tools/arch/arm64/include/asm/sysreg.h
1042
#define POE_X UL(0x2)
tools/arch/arm64/include/asm/sysreg.h
1043
#define POE_RX UL(0x3)
tools/arch/arm64/include/asm/sysreg.h
1044
#define POE_W UL(0x4)
tools/arch/arm64/include/asm/sysreg.h
1045
#define POE_RW UL(0x5)
tools/arch/arm64/include/asm/sysreg.h
1046
#define POE_WX UL(0x6)
tools/arch/arm64/include/asm/sysreg.h
1047
#define POE_RWX UL(0x7)
tools/arch/arm64/include/asm/sysreg.h
1048
#define POE_MASK UL(0xf)
tools/arch/arm64/include/asm/sysreg.h
885
#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
tools/arch/arm64/include/asm/sysreg.h
886
#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
tools/arch/arm64/include/asm/sysreg.h
887
#define MAIR_ATTR_NORMAL_NC UL(0x44)
tools/arch/arm64/include/asm/sysreg.h
888
#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
tools/arch/arm64/include/asm/sysreg.h
889
#define MAIR_ATTR_NORMAL UL(0xff)
tools/arch/arm64/include/asm/sysreg.h
890
#define MAIR_ATTR_MASK UL(0xff)
tools/arch/arm64/include/asm/sysreg.h
974
#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
tools/arch/arm64/include/asm/sysreg.h
975
#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
tools/arch/riscv/include/asm/csr.h
12
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
tools/arch/riscv/include/asm/csr.h
121
#define HSTATUS_VSXL _AC(0x300000000, UL)
tools/arch/riscv/include/asm/csr.h
124
#define HSTATUS_VTSR _AC(0x00400000, UL)
tools/arch/riscv/include/asm/csr.h
125
#define HSTATUS_VTW _AC(0x00200000, UL)
tools/arch/riscv/include/asm/csr.h
126
#define HSTATUS_VTVM _AC(0x00100000, UL)
tools/arch/riscv/include/asm/csr.h
127
#define HSTATUS_VGEIN _AC(0x0003f000, UL)
tools/arch/riscv/include/asm/csr.h
129
#define HSTATUS_HU _AC(0x00000200, UL)
tools/arch/riscv/include/asm/csr.h
13
#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
tools/arch/riscv/include/asm/csr.h
130
#define HSTATUS_SPVP _AC(0x00000100, UL)
tools/arch/riscv/include/asm/csr.h
131
#define HSTATUS_SPV _AC(0x00000080, UL)
tools/arch/riscv/include/asm/csr.h
132
#define HSTATUS_GVA _AC(0x00000040, UL)
tools/arch/riscv/include/asm/csr.h
133
#define HSTATUS_VSBE _AC(0x00000020, UL)
tools/arch/riscv/include/asm/csr.h
136
#define HGATP_MODE_OFF _AC(0, UL)
tools/arch/riscv/include/asm/csr.h
137
#define HGATP_MODE_SV32X4 _AC(1, UL)
tools/arch/riscv/include/asm/csr.h
138
#define HGATP_MODE_SV39X4 _AC(8, UL)
tools/arch/riscv/include/asm/csr.h
139
#define HGATP_MODE_SV48X4 _AC(9, UL)
tools/arch/riscv/include/asm/csr.h
14
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
tools/arch/riscv/include/asm/csr.h
140
#define HGATP_MODE_SV57X4 _AC(10, UL)
tools/arch/riscv/include/asm/csr.h
15
#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
tools/arch/riscv/include/asm/csr.h
16
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
tools/arch/riscv/include/asm/csr.h
168
#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \
tools/arch/riscv/include/asm/csr.h
169
(_AC(1, UL) << IRQ_S_TIMER) | \
tools/arch/riscv/include/asm/csr.h
17
#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
tools/arch/riscv/include/asm/csr.h
170
(_AC(1, UL) << IRQ_S_EXT) | \
tools/arch/riscv/include/asm/csr.h
171
(_AC(1, UL) << IRQ_PMU_OVF))
tools/arch/riscv/include/asm/csr.h
18
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
tools/arch/riscv/include/asm/csr.h
197
#define ENVCFG_CBZE (_AC(1, UL) << 7)
tools/arch/riscv/include/asm/csr.h
198
#define ENVCFG_CBCFE (_AC(1, UL) << 6)
tools/arch/riscv/include/asm/csr.h
20
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
tools/arch/riscv/include/asm/csr.h
200
#define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)
tools/arch/riscv/include/asm/csr.h
201
#define ENVCFG_CBIE_ILL _AC(0x0, UL)
tools/arch/riscv/include/asm/csr.h
202
#define ENVCFG_CBIE_FLUSH _AC(0x1, UL)
tools/arch/riscv/include/asm/csr.h
203
#define ENVCFG_CBIE_INV _AC(0x3, UL)
tools/arch/riscv/include/asm/csr.h
204
#define ENVCFG_FIOM _AC(0x1, UL)
tools/arch/riscv/include/asm/csr.h
21
#define SR_FS_OFF _AC(0x00000000, UL)
tools/arch/riscv/include/asm/csr.h
22
#define SR_FS_INITIAL _AC(0x00002000, UL)
tools/arch/riscv/include/asm/csr.h
23
#define SR_FS_CLEAN _AC(0x00004000, UL)
tools/arch/riscv/include/asm/csr.h
24
#define SR_FS_DIRTY _AC(0x00006000, UL)
tools/arch/riscv/include/asm/csr.h
26
#define SR_VS _AC(0x00000600, UL) /* Vector Status */
tools/arch/riscv/include/asm/csr.h
27
#define SR_VS_OFF _AC(0x00000000, UL)
tools/arch/riscv/include/asm/csr.h
28
#define SR_VS_INITIAL _AC(0x00000200, UL)
tools/arch/riscv/include/asm/csr.h
29
#define SR_VS_CLEAN _AC(0x00000400, UL)
tools/arch/riscv/include/asm/csr.h
30
#define SR_VS_DIRTY _AC(0x00000600, UL)
tools/arch/riscv/include/asm/csr.h
32
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
tools/arch/riscv/include/asm/csr.h
33
#define SR_XS_OFF _AC(0x00000000, UL)
tools/arch/riscv/include/asm/csr.h
34
#define SR_XS_INITIAL _AC(0x00008000, UL)
tools/arch/riscv/include/asm/csr.h
35
#define SR_XS_CLEAN _AC(0x00010000, UL)
tools/arch/riscv/include/asm/csr.h
36
#define SR_XS_DIRTY _AC(0x00018000, UL)
tools/arch/riscv/include/asm/csr.h
41
#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
tools/arch/riscv/include/asm/csr.h
43
#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
tools/arch/riscv/include/asm/csr.h
463
# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF)
tools/arch/riscv/include/asm/csr.h
468
#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
tools/arch/riscv/include/asm/csr.h
469
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
tools/arch/riscv/include/asm/csr.h
47
#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
tools/arch/riscv/include/asm/csr.h
470
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
tools/arch/riscv/include/asm/csr.h
48
#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
tools/arch/riscv/include/asm/csr.h
49
#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
tools/arch/riscv/include/asm/csr.h
54
#define SATP_PPN _AC(0x003FFFFF, UL)
tools/arch/riscv/include/asm/csr.h
55
#define SATP_MODE_32 _AC(0x80000000, UL)
tools/arch/riscv/include/asm/csr.h
59
#define SATP_ASID_MASK _AC(0x1FF, UL)
tools/arch/riscv/include/asm/csr.h
61
#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
tools/arch/riscv/include/asm/csr.h
62
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
tools/arch/riscv/include/asm/csr.h
63
#define SATP_MODE_48 _AC(0x9000000000000000, UL)
tools/arch/riscv/include/asm/csr.h
64
#define SATP_MODE_57 _AC(0xa000000000000000, UL)
tools/arch/riscv/include/asm/csr.h
68
#define SATP_ASID_MASK _AC(0xFFFF, UL)
tools/arch/riscv/include/asm/csr.h
72
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
tools/include/linux/bits.h
8
#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
tools/include/linux/mm.h
10
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
tools/include/linux/poison.h
13
# define POISON_POINTER_DELTA _AC(CONFIG_ILLEGAL_POINTER_VALUE, UL)
tools/include/uapi/linux/const.h
25
#define _UL(x) (_AC(x, UL))
tools/include/vdso/bits.h
7
#define BIT(nr) (UL(1) << (nr))
tools/perf/util/kvm-stat-arch/riscv_trap_types.h
6
#define CAUSE_IRQ_FLAG(xlen) (_AC(1, UL) << (xlen - 1))
tools/testing/selftests/kvm/include/arm64/processor.h
100
#define TCR_IPS_40_BITS (UL(2) << TCR_IPS_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
101
#define TCR_IPS_36_BITS (UL(1) << TCR_IPS_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
103
#define TCR_TBI1 (UL(1) << 38)
tools/testing/selftests/kvm/include/arm64/processor.h
104
#define TCR_HA (UL(1) << 39)
tools/testing/selftests/kvm/include/arm64/processor.h
105
#define TCR_DS (UL(1) << 59)
tools/testing/selftests/kvm/include/arm64/processor.h
120
#define PTE_SHARED (UL(3) << 8) /* SH[1:0], inner shareable */
tools/testing/selftests/kvm/include/arm64/processor.h
47
#define MAIR_ATTR_DEVICE_GRE UL(0x0c)
tools/testing/selftests/kvm/include/arm64/processor.h
48
#define MAIR_ATTR_NORMAL_WT UL(0xbb)
tools/testing/selftests/kvm/include/arm64/processor.h
67
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
tools/testing/selftests/kvm/include/arm64/processor.h
70
#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
71
#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
72
#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
73
#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
74
#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
77
#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
78
#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
79
#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
80
#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
81
#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
84
#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
85
#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
88
#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
89
#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
90
#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
91
#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
94
#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
97
#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
98
#define TCR_IPS_52_BITS (UL(6) << TCR_IPS_SHIFT)
tools/testing/selftests/kvm/include/arm64/processor.h
99
#define TCR_IPS_48_BITS (UL(5) << TCR_IPS_SHIFT)
tools/testing/selftests/powerpc/primitives/asm/asm-const.h
11
# define __ASM_CONST(x) x##UL
