UART_MCR
udbg_uart_out(UART_MCR, 0x3);
if (udbg_uart_in(UART_MCR) & 0x80)
out_8(avr_addr + UART_MCR, 0);
speakup_info.port_tts + UART_MCR);
int old = inb(speakup_info.port_tts + UART_MCR);
outb((old & ~clear) | set, speakup_info.port_tts + UART_MCR);
outb(UART_MCR_DTR | UART_MCR_RTS, ser->port + UART_MCR);
outb(0, iobase + UART_MCR);
outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase + UART_MCR);
outb(0, iobase + UART_MCR);
soutp(UART_MCR, hardware[type].off);
soutp(UART_MCR, hardware[type].on);
soutp(UART_MCR, hardware[type].on);
soutp(UART_MCR, hardware[type].off);
sdio_out(port, UART_MCR, mcr);
save_mcr = regs[UART_MCR];
regs[UART_MCR] = (UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
regs[UART_MCR] = save_mcr;
outb(info->MCR, info->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
oldmcr = inb(io + UART_MCR);
outb(0, io + UART_MCR);
if (inb(io + UART_MCR) != 0) {
outb(oldmcr, io + UART_MCR);
mcr = inb(mp->ioaddr + UART_MCR);
outb(mcr, mp->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
outb(info->MCR, info->ioaddr + UART_MCR);
serial_out(up, UART_MCR, value);
mctrl = serial_in(up, UART_MCR);
mcr = serial_port_in(p, UART_MCR);
serial_port_out(p, UART_MCR, mcr);
status = serial_port_in(p, UART_MCR);
serial_port_out(p, UART_MCR, status);
serial_port_out(p, UART_MCR, up->mcr);
serial_port_out(p, UART_MCR, up->mcr | UART_MCR_LOOP);
unsigned int mcr = serial_port_in(p, UART_MCR);
serial_port_out(p, UART_MCR, mcr);
serial8250_early_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
case UART_MCR:
serial8250_em_serial_out_helper(p, UART_MCR, mcr);
case UART_MCR:
case UART_MCR: /* MCR @ 0x14 (+1) */
case UART_MCR: /* MCR @ 0x14 (+1) */
mcr = serial8250_em_serial_in(p, UART_MCR);
writeb(UART_MCR_OUT1, p + UART_MCR);
early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
case UART_MCR:
case UART_MCR:
case UART_MCR:
serial_out(up, UART_MCR, UART_MCR_RTS);
qmcr = inb(base + UART_MCR);
outb(qmcr, base + UART_MCR);
[UART_MCR] = 6,
[UART_MCR] = 6,
case UART_MCR:
case UART_MCR:
serial_out(up, UART_MCR, up->mcr);
serial_out(up, UART_MCR, up->mcr);
old_mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr);
up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
serial_out(up, UART_MCR, up->mcr);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
iowrite8(mcr, priv->membase + UART_MCR);
"MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
serial_out(up, UART_MCR, mcr);
tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
tegra_uart_write(tup, mcr, UART_MCR);
tegra_uart_write(tup, mcr, UART_MCR);
tegra_uart_write(tup, mcr, UART_MCR);
mcr = tegra_uart_read(tup, UART_MCR);
mcr = tegra_uart_read(tup, UART_MCR);
save_mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
serial_out(up, UART_MCR, save_mcr);
serial_out(up, UART_MCR, save_mcr);
if (offset == UART_MCR)
serial_out(up, UART_MCR, mcr);
ark3116_write_reg(serial, UART_MCR, 0);
ark3116_write_reg(port->serial, UART_MCR, priv->mcr);
status = qt2_setregister(dev, port_priv->device_port, UART_MCR,
r = qt2_getregister(dev, port_priv->device_port, UART_MCR, d);
UART_MCR, 0) < 0)
result = ssu100_setregister(dev, 0, UART_MCR, urb_value);
r = ssu100_getregister(dev, 0, UART_MCR, d);
if (ssu100_setregister(dev, 0, UART_MCR, 0) < 0)
case UART_MCR:
(mdev_state->s[index].uart_reg[UART_MCR] &
case UART_MCR:
if (mdev_state->s[index].uart_reg[UART_MCR] &
,uart->base + UART_MCR); /* Modem Control Register */
uart->base + UART_MCR);
uart->base + UART_MCR);
,uart->base + UART_MCR); /* Modem Control Register */
uart->base + UART_MCR);
uart->base + UART_MCR);
outb(UART_MCR_RTS | (0&UART_MCR_DTR), uart->base + UART_MCR);
outb(UART_MCR_RTS | UART_MCR_DTR, uart->base + UART_MCR);