UART_FCR
out_8(reg_base + (UART_FCR << reg_shift), 0x06);
udbg_uart_out(UART_FCR, 0x7);
#define UART_IIR UART_FCR
out_8(avr_addr + UART_FCR, 0);
out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */
out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */
out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO |
outb(1, speakup_info.port_tts + UART_FCR); /* Turn FIFO On */
sdio_out(port, UART_FCR, fcr);
sdio_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
sdio_out(port, UART_FCR, UART_FCR_ENABLE_FIFO |
sdio_out(port, UART_FCR, 0);
sdio_out(port, UART_FCR, UART_FCR_ENABLE_FIFO |
sdio_out(port, UART_FCR, 0);
port->ioaddr + UART_FCR);
port->ioaddr + UART_FCR);
outb(info->FCR, info->ioaddr + UART_FCR);
outb(fcr, info->ioaddr + UART_FCR);
info->ioaddr + UART_FCR);
serial_port_out(p, UART_FCR, up->fcr);
serial8250_early_out(port, UART_FCR, 0); /* no fifo */
case UART_FCR:
early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
case UART_FCR:
case UART_FCR:
if (offset == UART_FCR && (value & UART_FCR_ENABLE_FIFO))
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
serial_out(up, UART_FCR, up->fcr);
serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_port_out(port, UART_FCR, up->fcr);
serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_port_out(port, UART_FCR, up->fcr);
serial_out(up, UART_FCR, up->fcr);
serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(p, UART_FCR, 0);
serial_out(p, UART_FCR, p->fcr);
old_fcr = serial_in(up, UART_FCR);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, old_fcr);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
[UART_FCR] = 4,
case UART_FCR:
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
serial_out(up, UART_FCR, up->fcr);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, up->fcr);
iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
priv->membase + UART_FCR);
iowrite8(priv->fcr, priv->membase + UART_FCR);
iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
priv->membase + UART_FCR);
iowrite8(fcr, priv->membase + UART_FCR);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, fcr);
tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
tegra_uart_write(tup, fcr, UART_FCR);
tegra_uart_write(tup, fcr, UART_FCR);
tegra_uart_write(tup, fcr, UART_FCR);
tegra_uart_write(tup, fcr, UART_FCR);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR,
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR,
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
serial_out(up, UART_FCR, 0);
serial_out(up, UART_FCR, fcr); /* set fcr */
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_FCR, fcr); /* set fcr */
ark3116_write_reg(serial, UART_FCR, 0);
ark3116_write_reg(serial, UART_FCR, 0);
ark3116_write_reg(serial, UART_FCR, UART_FCR_DMA_SELECT);
ark3116_write_reg(serial, UART_FCR, 0);
ark3116_write_reg(port->serial, UART_FCR, UART_FCR_DMA_SELECT);
case UART_FCR:
,uart->base + UART_FCR); /* FIFO Control Register */