drivers/gpu/drm/i915/gt/intel_engine_cs.c

75

{ .graphics_ver = 6, .base = BLT_RING_BASE }

drivers/gpu/drm/i915/gt/intel_engine_regs.h

41

#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

42

#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

43

#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))

drivers/gpu/drm/i915/gt/intel_rc6.c

465

(intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&

drivers/gpu/drm/i915/gvt/handlers.c

2189

MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \

drivers/gpu/drm/i915/gvt/handlers.c

2818

MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/mmio_context.c

139

{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

drivers/gpu/drm/i915/gvt/mmio_context.c

140

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

drivers/gpu/drm/i915/gvt/mmio_context.c

141

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

142

{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

drivers/gpu/drm/i915/gvt/mmio_context.c

143

{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */

drivers/gpu/drm/i915/gvt/mmio_context.c

85

{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

drivers/gpu/drm/i915/gvt/mmio_context.c

86

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

drivers/gpu/drm/i915/gvt/mmio_context.c

87

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

88

{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

drivers/gpu/drm/i915/gvt/mmio_context.c

89

{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */

drivers/gpu/drm/i915/i915_cmd_parser.c

648

REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

681

REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

688

REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

689

REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

690

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),

drivers/gpu/drm/i915/i915_cmd_parser.c

691

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),

drivers/gpu/drm/i915/i915_cmd_parser.c

692

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),

drivers/gpu/drm/i915/i915_cmd_parser.c

693

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),

drivers/gpu/drm/i915/i915_cmd_parser.c

694

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),

drivers/gpu/drm/i915/i915_cmd_parser.c

695

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),

drivers/gpu/drm/i915/i915_cmd_parser.c

696

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),

drivers/gpu/drm/i915/i915_cmd_parser.c

697

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),

drivers/gpu/drm/i915/i915_cmd_parser.c

698

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),

drivers/gpu/drm/i915/i915_cmd_parser.c

699

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),

drivers/gpu/drm/i915/i915_cmd_parser.c

700

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),

drivers/gpu/drm/i915/i915_cmd_parser.c

701

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),

drivers/gpu/drm/i915/i915_cmd_parser.c

702

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),

drivers/gpu/drm/i915/i915_cmd_parser.c

703

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),

drivers/gpu/drm/i915/i915_cmd_parser.c

704

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),

drivers/gpu/drm/i915/i915_cmd_parser.c

705

REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1262

MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

54

MMIO_F(prefix(BLT_RING_BASE), s); \

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

618

MMIO_D(ECOSKPD(BLT_RING_BASE));

drivers/gpu/drm/xe/xe_hw_engine.c

71

.mmio_base = BLT_RING_BASE,