TRB_TYPE
priv_ep->trb_pool[0].control = cpu_to_le32(TRB_CYCLE | TRB_TYPE(TRB_NORMAL));
TRB_TYPE(TRB_NORMAL));
TRB_TYPE(TRB_NORMAL));
control = TRB_TYPE(TRB_NORMAL) | TRB_CYCLE |
TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit);
control |= TRB_TYPE(TRB_NORMAL);
link_trb->control = cpu_to_le32(TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE);
TRB_TYPE(TRB_LINK) | TRB_CHAIN);
#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
cpu_to_le32(TRB_TYPE(TRB_LINK)))
cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
val |= TRB_TYPE(TRB_LINK);
trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
case TRB_TYPE(TRB_COMPLETION):
case TRB_TYPE(TRB_PORT_STATUS):
case TRB_TYPE(TRB_TRANSFER):
case TRB_TYPE(TRB_SETUP):
case TRB_TYPE(TRB_ENDPOINT_NRDY):
case TRB_TYPE(TRB_HC_EVENT): {
case TRB_TYPE(TRB_MFINDEX_WRAP):
case TRB_TYPE(TRB_DRB_OVERFLOW):
field = TRB_TYPE(TRB_NORMAL);
field = TRB_TYPE(TRB_TR_NOOP) | TRB_IOC;
field = TRB_TYPE(TRB_DATA);
field = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
TRB_TYPE(TRB_STATUS) | pdev->setup_speed);
field = TRB_TYPE(TRB_ISOC) | TRB_TLBPC(last_burst_pkt) |
field = TRB_TYPE(TRB_NORMAL) | ep_ring->cycle_state;
cdnsp_queue_command(pdev, 0, 0, 0, TRB_TYPE(trb_type) |
TRB_TYPE(TRB_ADDR_DEV) |
cdnsp_queue_command(pdev, 0, 0, 0, TRB_TYPE(TRB_RESET_DEV) |
TRB_TYPE(TRB_CONFIG_EP) |
EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_STOP_RING));
u32 type = TRB_TYPE(TRB_SET_DEQ);
TRB_TYPE(TRB_RESET_EP));
cdnsp_queue_command(pdev, 0, 0, 0, TRB_TYPE(TRB_HALT_ENDPOINT) |
TRB_TYPE(TRB_FORCE_HEADER) | SET_PORT_ID(2));
link_trb->field[3] = cpu_to_le32(TRB_TYPE(TRB_LINK)) | cpu_to_le32(LINK_TOGGLE);
control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
case TRB_TYPE(TRB_PORT_STATUS):
case TRB_TYPE(TRB_TRANSFER):
TRB_TYPE(TRB_NORMAL));
TRB_TYPE(TRB_NORMAL));
TRB_TYPE(TRB_NORMAL));
link_trb->control = cpu_to_le32(TRB_CYCLE | TRB_TYPE(TRB_LINK) |
TRB_TYPE(TRB_LINK));
TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit);
control = TRB_TYPE(TRB_NORMAL);
control = TRB_TYPE(TRB_NORMAL) | ring->pcs | TRB_ISP;
control = ring->pcs | TRB_TYPE(TRB_LINK) | TRB_CHAIN
trb->control = cpu_to_le32((hw_ccs ? TRB_CYCLE : 0) | TRB_TYPE(TRB_NORMAL));
TRB_TYPE(TRB_LINK) | TRB_CHAIN);
case TRB_TYPE(TRB_PORT_STATUS):
case TRB_TYPE(TRB_TRANSFER):
trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
trb->link.control = cpu_to_le32(LINK_TOGGLE | TRB_TYPE(TRB_LINK));
val |= TRB_TYPE(TRB_LINK);
trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
field = TRB_TYPE(TRB_NORMAL);
field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
field = TRB_TYPE(TRB_TR_NOOP) | ep_ring->cycle_state;
field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
field = TRB_ISP | TRB_TYPE(TRB_DATA);
field = TRB_TYPE(TRB_DATA);
field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
field = TRB_TYPE(TRB_ISOC) |
field = TRB_TYPE(TRB_NORMAL) |
TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
TRB_TYPE(TRB_GET_BW) | DEV_SPEED_FOR_TRB(dev_speed),
TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
u32 type = TRB_TYPE(TRB_STOP_RING);
u32 type = TRB_TYPE(TRB_RESET_EP);
EP_INDEX_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
TRB_TYPE(TRB_NEC_GET_FW));
#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
cpu_to_le32(TRB_TYPE(TRB_LINK)))
cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))