drivers/clocksource/timer-stm32.c

114

writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);

drivers/counter/stm32-timer-cnt.c

144

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/counter/stm32-timer-cnt.c

152

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);

drivers/counter/stm32-timer-cnt.c

207

*enable = cr1 & TIM_CR1_CEN;

drivers/counter/stm32-timer-cnt.c

221

if (!(cr1 & TIM_CR1_CEN)) {

drivers/counter/stm32-timer-cnt.c

229

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,

drivers/counter/stm32-timer-cnt.c

230

TIM_CR1_CEN);

drivers/counter/stm32-timer-cnt.c

233

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/counter/stm32-timer-cnt.c

234

if (cr1 & TIM_CR1_CEN)

drivers/counter/stm32-timer-cnt.c

811

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/iio/trigger/stm32-timer-trigger.c

181

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

198

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

254

if (cr1 & TIM_CR1_CEN) {

drivers/iio/trigger/stm32-timer-trigger.c

466

*val = (dat & TIM_CR1_CEN) ? 1 : 0;

drivers/iio/trigger/stm32-timer-trigger.c

510

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

512

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

836

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

857

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

394

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

418

ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

483

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

528

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);