TCR
#define TCR1 TCR
#define TCR1 TCR
(dma_base_addr(chan->chan) + TCR));
return __raw_readl(dma_base_addr(chan->chan) + TCR)
[TCR] = 0,
sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
if (reg_nr == TCR)
sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
sh_tmu_read(ch, TCR);
sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
if (reg_nr == TCR)
keystone_timer_writel(tcr, TCR);
tcr = keystone_timer_readl(TCR);
keystone_timer_writel(tcr, TCR);
keystone_timer_writel(0, TCR);
tcr = keystone_timer_readl(TCR);
keystone_timer_writel(off, TCR);
sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
(sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
volatile u_char TCR; /* Timer Control Register */
macb_writel(lp, TCR, skb->len);
outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR );
outw( TCR_CLEAR, ioaddr + TCR );
outw( TCR_NORMAL, ioaddr + TCR );
outb( TCR_CLEAR, ioaddr + TCR );
mask_bits(0xff00, ioaddr + TCR);
outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
outw(TCR_CLEAR, ioaddr + TCR);
TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR);
outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR);
tmp = inw(ioaddr + TCR);
tmp = inw(ioaddr + TCR);
outw(tmp, ioaddr + TCR);
BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
td_ptr->tdesc1.TCR = TCR0_TIC;
td_ptr->tdesc1.TCR |= TCR0_VETAG;
td_ptr->tdesc1.TCR |= TCR0_TCPCK;
td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
td_ptr->tdesc1.TCR |= TCR0_IPCK;
BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
u8 TCR;
volatile u8 TCR;
set_registers(dev, TCR, 1, &tcr);
sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
cpustatus = rtl_read_byte(rtlpriv, TCR);
cpustatus = rtl_read_byte(rtlpriv, TCR);
cpustatus = rtl_read_byte(rtlpriv, TCR);
cpustatus = rtl_read_byte(rtlpriv, TCR);
tmpu4b = rtl_read_dword(rtlpriv, TCR);
rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
cpustatus = rtl_read_byte(rtlpriv, TCR);
temp = rtl_read_dword(rtlpriv, TCR);
rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
rtl_write_byte(rtlpriv, TCR, 0);
rtl_write_byte(rtlpriv, TCR, 0);
tmpu1b = rtl_read_byte(rtlpriv, TCR);
rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
spi_readl(as, TCR), spi_readl(as, RCR));
spi_writel(as, TCR, 0);
spi_writel(as, TCR, len);
value = rd_reg16(info, TCR);
wr_reg16(info, TCR, value);
unsigned short val = rd_reg16(info, TCR);
wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
wr_reg16(info, TCR, val); /* clear reset bit */
val = rd_reg16(info, TCR);
wr_reg16(info, TCR, val);
wr_reg16(info, TCR,
(unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
wr_reg16(info, TCR, val);
wr_reg16(info, TCR, val);
tcr = rd_reg16(info, TCR);
wr_reg16(info, TCR, tcr);
wr_reg16(info, TCR,
(unsigned short)(rd_reg16(info, TCR) | BIT1));
iowrite32(0, davinci_wdt->base + TCR);
iowrite32(0, davinci_wdt->base + TCR);
iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
i2s_write_reg(dev->i2s_base, TCR(ch_reg),
kmb_i2s->i2s_base + TCR(ch_reg));
copy_el2_to_el1(TCR);