arch/arm/mach-omap1/board-ams-delta.c

301

.size = SZ_256K },

arch/arm/mach-omap1/board-ams-delta.c

303

.offset = 3 * SZ_1M + SZ_512K + SZ_256K,

arch/arm/mach-omap1/board-ams-delta.c

304

.size = SZ_256K },

arch/arm/mach-omap1/board-ams-delta.c

307

.size = SZ_256K },

arch/arm/mach-omap1/board-ams-delta.c

309

.offset = 4 * SZ_1M + 1 * SZ_256K,

arch/arm/mach-omap1/board-ams-delta.c

312

.offset = 32 * SZ_1M - 3 * SZ_256K,

arch/arm/mach-omap1/board-ams-delta.c

313

.size = 3 * SZ_256K },

arch/arm/mach-orion5x/kurobox_pro-setup.c

37

#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K

arch/arm/mach-orion5x/terastation_pro2-setup.c

44

#define TSP2_NOR_BOOT_SIZE SZ_256K

arch/arm/mach-pxa/pxa3xx.c

62

#define ISRAM_SIZE SZ_256K

arch/arm/mach-shmobile/pm-rcar-gen2.c

55

if (!request_mem_region(0, SZ_256K, "Boot Area")) {

arch/arm/mach-shmobile/pm-rcar-gen2.c

84

if (res.start & (SZ_256K - 1) ||

arch/arm/mach-tegra/iomap.h

17

#define TEGRA_IRAM_SIZE SZ_256K

arch/arm/mach-tegra/iomap.h

86

#define TEGRA_CSITE_SIZE SZ_256K

arch/arm/mach-tegra/iomap.h

99

#define IO_IRAM_SIZE SZ_256K

arch/arm/mach-versatile/integrator-hardware.h

42

#define INTEGRATOR_SSRAM_SIZE SZ_256K

arch/arm/mm/cache-l2x0.c

1070

ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);

arch/arm/mm/dma-mapping.c

185

#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K

arch/arm64/kernel/signal.c

155

#define SIGFRAME_MAXSZ SZ_256K

arch/mips/loongson64/init.c

106

SZ_256K);

arch/powerpc/mm/book3s32/mmu.c

33

u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};

arch/sh/boards/board-edosk7760.c

36

.size = SZ_256K,

arch/sh/drivers/pci/pci-sh7780.c

367

__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,

arch/sh/drivers/pci/pcie-sh7786.c

462

mask = (roundup_pow_of_two(size) / SZ_256K) - 1;

arch/x86/kernel/cpu/cpuid_0x2_table.c

29

CACHE_ENTRY(0x21, CACHE_L2, SZ_256K ), /* 8-way set assoc, 64 byte line size */

arch/x86/kernel/cpu/cpuid_0x2_table.c

39

CACHE_ENTRY(0x3c, CACHE_L2, SZ_256K ), /* 4-way set assoc, sectored cache, 64 byte line size */

arch/x86/kernel/cpu/cpuid_0x2_table.c

42

CACHE_ENTRY(0x3f, CACHE_L2, SZ_256K ), /* 2-way set assoc, 64 byte line size */

arch/x86/kernel/cpu/cpuid_0x2_table.c

44

CACHE_ENTRY(0x42, CACHE_L2, SZ_256K ), /* 4-way set assoc, 32 byte line size */

arch/x86/kernel/cpu/cpuid_0x2_table.c

63

CACHE_ENTRY(0x7a, CACHE_L2, SZ_256K ), /* 8-way set assoc, sectored cache, 64 byte line size */

arch/x86/kernel/cpu/cpuid_0x2_table.c

69

CACHE_ENTRY(0x82, CACHE_L2, SZ_256K ), /* 8-way set assoc, 32 byte line size */

arch/x86/kernel/setup.c

1023

e820__range_update(0x70000000ULL, SZ_256K, E820_TYPE_RAM, E820_TYPE_RESERVED);

drivers/clk/tegra/clk-tegra210.c

3768

dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);

drivers/clk/tegra/clk-tegra210.c

3774

vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);

drivers/firmware/qcom/qcom_qseecom_uefisecapp.c

820

pool_config.max_size = SZ_256K;

drivers/firmware/qcom/qcom_scm.c

2796

pool_config.max_size = SZ_256K;

drivers/firmware/tegra/bpmp-debugfs.c

392

return single_open_size(file, bpmp_debug_show, file, SZ_256K);

drivers/gpio/gpio-sloppy-logic-analyzer.c

35

#define GPIO_LA_DEFAULT_BUF_SIZE SZ_256K

drivers/gpu/drm/bridge/lontium-lt8713sx.c

113

if (lt8713sx->fw->size > SZ_256K - 1) {

drivers/gpu/drm/bridge/lontium-lt8713sx.c

119

lt8713sx->fw_buffer = kvmalloc(SZ_256K, GFP_KERNEL);

drivers/gpu/drm/bridge/lontium-lt8713sx.c

125

memset(lt8713sx->fw_buffer, 0xff, SZ_256K);

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

183

#define I830_BATCH_LIMIT SZ_256K

drivers/gpu/drm/i915/gt/intel_gt.c

702

GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);

drivers/gpu/drm/i915/gt/intel_migrate.c

319

ce->ring_size = SZ_256K;

drivers/gpu/drm/imagination/pvr_mmu.c

44

#elif (PVR_DEVICE_PAGE_SIZE == SZ_256K)

drivers/gpu/drm/msm/adreno/a2xx_catalog.c

21

.gmem = SZ_256K,

drivers/gpu/drm/msm/adreno/a3xx_catalog.c

31

.gmem = SZ_256K,

drivers/gpu/drm/msm/adreno/a4xx_catalog.c

21

.gmem = SZ_256K,

drivers/gpu/drm/msm/adreno/a5xx_catalog.c

102

.gmem = (SZ_256K + SZ_16K),

drivers/gpu/drm/msm/adreno/a5xx_catalog.c

69

.gmem = (SZ_256K + SZ_16K),

drivers/gpu/drm/msm/adreno/a5xx_catalog.c

87

.gmem = SZ_256K,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2308

SZ_256K - SZ_16K, 0x04000, "icache");

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2313

SZ_256K - SZ_16K, 0x44000, "dcache");

drivers/gpu/drm/xe/xe_eu_stall.c

707

stream->per_xecore_buf_size / SZ_256K);

drivers/gpu/tests/gpu_buddy_test.c

129

num_blocks = mm_size / SZ_256K;

drivers/gpu/tests/gpu_buddy_test.c

136

KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_8K, SZ_256K,

drivers/gpu/tests/gpu_buddy_test.c

144

KUNIT_EXPECT_TRUE(test, IS_ALIGNED(gpu_buddy_block_offset(block), SZ_256K));

drivers/gpu/tests/gpu_buddy_test.c

149

KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_16K, SZ_256K,

drivers/gpu/tests/gpu_buddy_test.c

157

KUNIT_EXPECT_TRUE(test, IS_ALIGNED(gpu_buddy_block_offset(block), SZ_256K));

drivers/gpu/tests/gpu_buddy_test.c

173

KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_16K, SZ_256K,

drivers/gpu/tests/gpu_buddy_test.c

181

KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_16K, SZ_256K,

drivers/gpu/tests/gpu_buddy_test.c

32

SZ_256K,

drivers/infiniband/hw/irdma/hw.c

28

.qplimit = SZ_256K,

drivers/infiniband/hw/mana/mana_ib.h

21

(SZ_4K | SZ_8K | SZ_16K | SZ_32K | SZ_64K | SZ_128K | SZ_256K | \

drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c

22

#define VP8_SEG_ID_SZ SZ_256K

drivers/misc/bcm-vk/bcm_vk_dev.c

581

max_buf = SZ_256K;

drivers/mmc/core/sd.c

55

SZ_128K / 512, SZ_256K / 512, SZ_512K / 512, SZ_1M / 512,

drivers/mtd/nand/raw/nand_hynix.c

646

memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /

drivers/mtd/nand/raw/nand_hynix.c

648

mtd->erasesize = SZ_512K + SZ_256K;

drivers/mtd/nand/raw/nand_ids.c

34

SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

37

SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

40

SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

66

SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},

drivers/mtd/spi-nor/macronix.c

108

.size = SZ_256K,

drivers/mtd/spi-nor/macronix.c

161

.size = SZ_256K,

drivers/mtd/spi-nor/micron-st.c

263

.size = SZ_256K,

drivers/mtd/spi-nor/micron-st.c

281

.sector_size = SZ_256K,

drivers/mtd/spi-nor/micron-st.c

296

.size = SZ_256K,

drivers/mtd/spi-nor/micron-st.c

320

.sector_size = SZ_256K,

drivers/mtd/spi-nor/micron-st.c

365

.size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

865

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

872

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

891

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

899

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

907

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

916

.sector_size = SZ_256K,

drivers/mtd/spi-nor/spansion.c

923

.sector_size = SZ_256K,

drivers/mtd/spi-nor/sst.c

67

.size = SZ_256K,

drivers/mtd/spi-nor/sst.c

93

.size = SZ_256K,

drivers/mtd/spi-nor/winbond.c

163

.size = SZ_256K,

drivers/mtd/spi-nor/winbond.c

193

.size = SZ_256K,

drivers/mtd/spi-nor/winbond.c

236

.size = SZ_256K,

drivers/mtd/spi-nor/winbond.c

246

.size = SZ_256K,

drivers/net/ethernet/freescale/enetc/enetc.h

76

#define ENETC_LSO_MAX_DATA_LEN SZ_256K

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

67

#define CMDQ_WQ_PAGE_SIZE SZ_256K

drivers/net/ethernet/huawei/hinic/hinic_hw_io.h

24

#define HINIC_DEFAULT_WQ_PAGE_SIZE SZ_256K

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

41

#define HINIC_SQ_PAGE_SIZE SZ_256K

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

42

#define HINIC_RQ_PAGE_SIZE SZ_256K

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1232

nfp_cpp_area_cache_add(cpp, SZ_256K);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

35

.max_qc_size = SZ_256K,

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

47

.max_qc_size = SZ_256K,

drivers/net/ethernet/ti/icssg/icssg_config.h

93

#define MSMC_RAM_BANK_SIZE SZ_256K

drivers/pci/controller/dwc/pcie-tegra194-acpi.c

32

pcie_ecam->iatu_base = cfg->win + SZ_256K;

drivers/pci/controller/dwc/pcie-tegra194-acpi.c

97

SZ_256K);

drivers/spi/spi-mt65xx.c

1255

dma_set_max_seg_size(dev, SZ_256K);

drivers/ufs/core/ufshcd.c

2707

WARN_ONCE(len > SZ_256K, "len = %#x\n", len);

fs/btrfs/defrag.c

1131

#define CLUSTER_SIZE (SZ_256K)

fs/btrfs/defrag.c

1403

extent_thresh = SZ_256K;

fs/btrfs/defrag.c

1437

(SZ_256K >> PAGE_SHIFT)) << PAGE_SHIFT) - 1;

fs/btrfs/tests/free-space-tests.c

432

ret = test_add_free_space_entry(cache, SZ_128M - SZ_256K, SZ_128K, 0);

fs/btrfs/tests/free-space-tests.c

466

if (!test_check_exists(cache, SZ_128M - SZ_256K, SZ_128K)) {

fs/btrfs/tests/free-space-tests.c

470

if (!test_check_exists(cache, SZ_128M + SZ_512K, SZ_256K)) {

fs/btrfs/tests/free-space-tests.c

489

if (test_check_exists(cache, SZ_128M + SZ_256K, SZ_256K)) {

fs/btrfs/tests/free-space-tests.c

498

if (test_check_exists(cache, SZ_128M, SZ_256K)) {

fs/btrfs/tests/free-space-tests.c

586

if (!test_check_exists(cache, SZ_128M - SZ_256K, SZ_1M)) {

fs/btrfs/tests/free-space-tests.c

599

if (offset != (SZ_128M - SZ_256K)) {

fs/btrfs/tests/free-space-tests.c

678

if (!test_check_exists(cache, SZ_128M - 768 * SZ_1K, SZ_256K)) {

fs/btrfs/tests/raid-stripe-tree-tests.c

156

if (len1 != SZ_256K) {

fs/btrfs/tests/raid-stripe-tree-tests.c

158

(u64)SZ_256K, len1);

fs/btrfs/tests/raid-stripe-tree-tests.c

174

logical3 += SZ_256K;

fs/btrfs/tests/raid-stripe-tree-tests.c

185

logical3 + SZ_256K, io_stripe.physical);

fs/btrfs/tests/raid-stripe-tree-tests.c

190

if (len3 != SZ_1M - SZ_256K) {

fs/btrfs/tests/raid-stripe-tree-tests.c

192

(u64)SZ_1M - SZ_256K, len3);

fs/btrfs/tests/raid-stripe-tree-tests.c

50

u64 hole_start = logical1 + SZ_256K;

fs/btrfs/volumes.h

322

#define BTRFS_DEFAULT_RR_MIN_CONTIG_READ (SZ_256K)

include/ufs/ufshci.h

468

#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K

mm/page_alloc.c

5911

batch = min(zone_managed_pages(zone) >> 12, SZ_256K / PAGE_SIZE);