arch/arm/mach-sa1100/ssp.c

120

while (Ser4SSSR & SSSR_RNE) {

arch/arm/mach-sa1100/ssp.c

127

} while (Ser4SSSR & SSSR_BSY);

arch/arm/mach-sa1100/ssp.c

174

Ser4SSSR = SSSR_ROR;

arch/arm/mach-sa1100/ssp.c

202

Ser4SSSR = SSSR_ROR;

arch/arm/mach-sa1100/ssp.c

27

unsigned int status = Ser4SSSR;

arch/arm/mach-sa1100/ssp.c

32

Ser4SSSR = SSSR_ROR;

arch/arm/mach-sa1100/ssp.c

55

while (!(Ser4SSSR & SSSR_TNF)) {

arch/arm/mach-sa1100/ssp.c

64

while (!(Ser4SSSR & SSSR_BSY)) {

arch/arm/mach-sa1100/ssp.c

92

while (!(Ser4SSSR & SSSR_RNE)) {