arch/arm/mach-keystone/keystone.c

143

.dma_zone_size = SZ_2G,

arch/arm/mach-omap2/board-generic.c

293

.dma_zone_size = SZ_2G,

arch/arm/mach-omap2/board-generic.c

342

.dma_zone_size = SZ_2G,

arch/arm/mach-omap2/board-generic.c

366

.dma_zone_size = SZ_2G,

arch/arm64/include/asm/memory.h

49

#define MODULES_VSIZE (SZ_2G)

arch/arm64/mm/gcs.c

37

rlimit(RLIMIT_STACK) / 2, SZ_2G));

arch/arm64/mm/init.c

462

BUILD_BUG_ON(MODULES_VSIZE < SZ_2G);

arch/arm64/mm/init.c

467

if (kernel_size < SZ_2G)

arch/arm64/mm/init.c

468

module_plt_base = kernel_end - SZ_2G;

arch/arm64/mm/init.c

483

module_plt_base = random_bounding_box(SZ_2G, min, max);

arch/arm64/mm/init.c

489

module_plt_base ? (SZ_2G - kernel_size) / PAGE_SIZE : 0);

arch/arm64/mm/init.c

513

fallback_end = module_plt_base + SZ_2G;

arch/arm64/mm/init.c

517

end = module_plt_base + SZ_2G;

arch/mips/mti-malta/malta-dtshim.c

122

mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_2G + SZ_256M);

arch/powerpc/include/asm/iommu.h

34

#define MIN_DDW_VPMEM_DMA_WINDOW SZ_2G

arch/powerpc/include/asm/uaccess.h

517

if (TASK_SIZE <= UL(SZ_2G) && border >= UL(SZ_2G))

arch/powerpc/kernel/trace/ftrace.c

654

if (reladdr >= (long)SZ_2G || reladdr < -(long long)SZ_2G) {

arch/powerpc/kernel/trace/ftrace_64_pg.c

735

if (reladdr >= SZ_2G || reladdr < -(long)SZ_2G) {

arch/powerpc/platforms/pseries/iommu.c

590

if (phb->dma_window_base_cur + phb->dma_window_size > SZ_2G) {

arch/powerpc/sysdev/dart_iommu.c

240

MEMBLOCK_LOW_LIMIT, SZ_2G,

arch/riscv/include/asm/pgtable.h

27

#define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1)

arch/riscv/include/asm/pgtable.h

59

#define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G)

arch/riscv/include/asm/pgtable.h

60

#define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G)

arch/riscv/mm/kasan_init.c

523

kasan_mem_to_shadow((const void *)MODULES_VADDR + SZ_2G));

arch/riscv/mm/ptdump.c

124

.end = SZ_2G,

arch/s390/boot/startup.c

313

vsize = round_up(SZ_2G + max_mappable, rte_size) +

arch/s390/boot/startup.c

604

amode31_lma = randomize_within_range(vmlinux.amode31_size, PAGE_SIZE, amode31_min, SZ_2G);

arch/s390/kernel/uv.c

66

uv_info.uv_base_stor_len, SZ_1M, SZ_2G,

arch/s390/kvm/pv.c

489

gmap_pv_destroy_range(kvm->arch.gmap, 0, gpa_to_gfn(SZ_2G), false);

drivers/accel/habanalabs/gaudi/gaudi.c

4583

min((u64)SZ_2G, prop->dram_end_address - cur_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10696

num_of_pkts = div64_u64(round_up(size, SZ_2G), SZ_2G);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10752

chunk_size = min_t(u64, SZ_2G, end_addr - cur_addr);

drivers/accel/habanalabs/goya/goya.c

4762

lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);

drivers/accel/habanalabs/goya/goya.c

4786

lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);

drivers/accel/habanalabs/goya/goya.c

4790

size -= SZ_2G;

drivers/accel/habanalabs/goya/goya.c

4791

addr += SZ_2G;

drivers/accel/ivpu/ivpu_hw.c

179

ivpu_hw_range_init(vdev, &vdev->hw->ranges.shave, 0x180000000, SZ_2G);

drivers/accel/ivpu/ivpu_hw.c

184

ivpu_hw_range_init(vdev, &vdev->hw->ranges.shave, 0x80000000, SZ_2G);

drivers/edac/synopsys_edac.c

429

linear_addr = linear_addr - SZ_32G + SZ_2G;

drivers/gpu/drm/etnaviv/etnaviv_drv.c

542

dma_set_max_seg_size(dev, SZ_2G);

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

909

if (cmdbuf_paddr >= SZ_2G)

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

910

priv->mmu_global->memory_base = SZ_2G;

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

913

} else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

917

priv->mmu_global->memory_base = SZ_2G;

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

509

mem = mock_region_create(i915, 0, SZ_2G, I915_GTT_PAGE_SIZE_4K, 0, 0);

drivers/gpu/drm/i915/selftests/intel_memory_region.c

1359

mem = mock_region_create(i915, 0, SZ_2G, I915_GTT_PAGE_SIZE_4K, 0, 0);

drivers/gpu/drm/i915/selftests/intel_memory_region.c

174

mem = mock_region_create(i915, 0, SZ_2G, I915_GTT_PAGE_SIZE_4K, 0, 0);

drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h

43

#define ROGUE_PM_MAX_FREELIST_SIZE SZ_2G

drivers/gpu/drm/tests/drm_buddy_test.c

862

u64 mm_size = SZ_8G + SZ_2G, size = SZ_8G + SZ_1G, min_block_size = SZ_8G;

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

155

KUNIT_EXPECT_EQ(test, SZ_2G, pf_profile_fair_ggtt(gt, 1));

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

159

KUNIT_EXPECT_EQ(test, SZ_2G + SZ_1G + SZ_512M, pf_profile_fair_ggtt(gt, 1));

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

168

u64 shareable = SZ_2G + SZ_1G + SZ_512M;

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

189

KUNIT_ASSERT_EQ(test, SZ_2G, pf_profile_fair_ggtt(gt, num_vfs));

drivers/gpu/drm/xe/xe_ttm_vram_mgr.c

383

xe_res_next(&cursor, min_t(u64, cursor.size, SZ_2G));

drivers/gpu/drm/xe/xe_ttm_vram_mgr.c

403

size_t size = min_t(u64, cursor.size, SZ_2G);

drivers/infiniband/hw/erdma/erdma_verbs.c

1253

SZ_2G - SZ_4K, false);

drivers/infiniband/hw/hns/hns_roce_main.c

840

dma_set_max_seg_size(dev, SZ_2G);

drivers/infiniband/hw/mana/main.c

715

caps->page_size_cap |= (SZ_4M | SZ_1G | SZ_2G);

drivers/infiniband/hw/mlx5/data_direct.c

77

dma_set_max_seg_size(&pdev->dev, SZ_2G);

drivers/infiniband/hw/usnic/usnic_ib_main.c

426

dma_set_max_seg_size(&dev->dev, SZ_2G);

drivers/iommu/generic_pt/kunit_iommu_pt.h

156

if (len <= SZ_2G)

drivers/iommu/generic_pt/kunit_iommu_pt.h

196

priv->info.pgsize_bitmap % (IS_32BIT ? SZ_2G : SZ_16G);

drivers/iommu/io-pgtable-arm-selftests.c

81

if (ops->iova_to_phys(ops, SZ_2G + 42))

drivers/iommu/io-pgtable-arm-v7s.c

846

if (ops->iova_to_phys(ops, SZ_2G + 42))

drivers/iommu/ipmmu-vmsa.c

810

mapping = arm_iommu_create_mapping(dev, SZ_1G, SZ_2G);

drivers/mailbox/mtk-cmdq-mailbox.c

843

.mminfra_offset = SZ_2G,

drivers/media/platform/allegro-dvt/allegro-core.c

90

#define MCU_CACHE_OFFSET SZ_2G

drivers/media/platform/mediatek/vpu/mtk_vpu.c

887

vpu->enable_4GB = !!(totalram_pages() > (SZ_2G >> PAGE_SHIFT));

drivers/media/platform/ti/omap3isp/isp.c

1938

mapping = arm_iommu_create_mapping(isp->dev, SZ_1G, SZ_2G);

drivers/mmc/host/sdhci-xenon.c

467

if (si.totalram * si.mem_unit > SZ_2G) {

drivers/mtd/nand/raw/loongson-nand-controller.c

702

if (chipsize == SZ_2G) {

drivers/pci/controller/cadence/pcie-cadence-host-common.c

21

[RP_BAR0] = _ULL(128 * SZ_2G),

drivers/pci/controller/cadence/pcie-cadence-host-common.c

22

[RP_BAR1] = SZ_2G,

drivers/pci/controller/pci-ftpci100.c

161

case SZ_2G:

drivers/pci/controller/pci-rcar-gen2.c

213

case SZ_2G:

drivers/pci/controller/pci-v3-semi.c

653

case SZ_2G:

drivers/pci/controller/pcie-brcmstb.c

1057

(pci_offset < SZ_4G && pci_offset > SZ_2G)) {

drivers/staging/media/atomisp/pci/mmu/isp_mmu.c

44

#define NR_PAGES_2GB (SZ_2G / PAGE_SIZE)

fs/btrfs/fs.h

72

#define BTRFS_MAX_TRIM_LENGTH SZ_2G

fs/btrfs/tests/chunk-allocation-tests.c

101

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

107

.min_hole_size = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

112

.expected_start = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

119

.min_hole_size = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

121

{ .start = SZ_2G, .len = SZ_1G },

fs/btrfs/tests/chunk-allocation-tests.c

126

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

132

.min_hole_size = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

138

.expected_start = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

145

.min_hole_size = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

152

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

158

.min_hole_size = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

173

{ .start = SZ_2G, .len = SZ_1G },

fs/btrfs/tests/chunk-allocation-tests.c

178

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

190

.expected_start = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

191

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

204

.expected_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

224

{ .start = 9ULL * SZ_1G, .len = SZ_2G },

fs/btrfs/tests/chunk-allocation-tests.c

349

.expected_pending_end = SZ_2G - 1,

fs/btrfs/tests/chunk-allocation-tests.c

355

.pending_extent = { 0, SZ_2G },

fs/btrfs/tests/chunk-allocation-tests.c

358

.expected_pending_end = SZ_2G - 1,

fs/btrfs/tests/chunk-allocation-tests.c

364

.pending_extent = { SZ_2G, SZ_1G },

fs/btrfs/tests/chunk-allocation-tests.c

366

.expected_pending_start = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

373

.pending_extent = { SZ_2G, SZ_1G },

fs/btrfs/tests/chunk-allocation-tests.c

379

.hole_len = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

380

.pending_extent = { SZ_1G, SZ_2G },

fs/btrfs/tests/chunk-allocation-tests.c

73

{ .start = 0, .len = SZ_2G },

fs/btrfs/tests/chunk-allocation-tests.c

76

.expected_start = SZ_2G,

fs/btrfs/tests/chunk-allocation-tests.c

97

{ .start = SZ_2G, .len = SZ_1G },

tools/testing/cxl/test/mem.c

21

#define DEV_SIZE SZ_2G

tools/testing/memblock/tests/basic_api.c

2404

ASSERT_FALSE(memblock_overlaps_region(&memblock.memory, SZ_2G, SZ_1M));

tools/testing/memblock/tests/basic_api.c

553

.base = SZ_2G,

tools/testing/selftests/kvm/mmu_stress_test.c

298

slot_size = SZ_2G;