drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

66

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

67

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

73

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

54

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

65

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h

71

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

71

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h

66

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

74

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h

33

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

77

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

77

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

74

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

76

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

76

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

75

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

76

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

75

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

66

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

66

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

65

.name = "sspp_1", .id = SSPP_VIG1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

196

case SSPP_VIG1:

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

490

[SSPP_VIG1] = { { 0, 3, 2 }, { 3, 4 } },

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

202

status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

90

status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

109

[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

197

[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

449

[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

668

[SSPP_VIG0] = 1, [SSPP_VIG1] = 9,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

282

case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

305

case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

433

case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

610

SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,