SSPP_VIG0
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
.name = "sspp_0", .id = SSPP_VIG0,
case SSPP_VIG0:
[SSPP_VIG0] = { { 0, 0, 0 }, { 3, 0 } },
} else if (pipe >= SSPP_VIG0 && pipe <= SSPP_VIG3) {
pipe_id = pipe - SSPP_VIG0;
status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
for (i = SSPP_VIG0; i < SSPP_MAX; i++)
seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0,
pipe->sspp->idx - SSPP_VIG0,
pdpu->pipe - SSPP_VIG0,
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
pdpu->pipe - SSPP_VIG0,
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
pdpu->pipe - SSPP_VIG0,
pdpu->pipe - SSPP_VIG0,
qos_params.num = pipe->sspp->idx - SSPP_VIG0;
[SSPP_VIG0] = 1,
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
[SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3;
case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0;
SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,