SET_BIT
SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) :
SET_BIT(csr, CE_NN_MODE_BITPOS) :
SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) :
SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) :
SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) :
SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) :
SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) :
SET_BIT(COHERENT));
SET_BIT(COHERENT));
*hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
SET_BIT(IC) |
SET_BIT(TYPE_ETH_WORK_MESSAGE);
SET_BIT(COHERENT));
ring_cfg[3] |= SET_BIT(X2_DEQINTEN);
ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM);
SET_BIT(Backplane);
SET_BIT(1000baseKX_Full);
SET_BIT(10000baseKX4_Full);
SET_BIT(40000baseKR4_Full);
SET_BIT(FIBRE);
SET_BIT(1000baseT_Full);
SET_BIT(1000baseX_Full);
SET_BIT(10000baseCR_Full);
SET_BIT(10000baseLR_Full);
SET_BIT(10000baseSR_Full);
SET_BIT(40000baseCR4_Full);
SET_BIT(40000baseSR4_Full);
SET_BIT(100000baseCR4_Full);
SET_BIT(100000baseSR4_Full);
SET_BIT(25000baseCR_Full);
SET_BIT(25000baseSR_Full);
SET_BIT(50000baseCR2_Full);
SET_BIT(TP);
SET_BIT(10baseT_Half);
SET_BIT(10baseT_Full);
SET_BIT(100baseT_Half);
SET_BIT(100baseT_Full);
SET_BIT(1000baseT_Half);
SET_BIT(1000baseT_Full);
SET_BIT(10000baseT_Full);
SET_BIT(Pause);
SET_BIT(Asym_Pause);
SET_BIT(Autoneg);
SET_BIT(Backplane);
SET_BIT(1000baseKX_Full);
SET_BIT(10000baseKX4_Full);
SET_BIT(40000baseKR4_Full);
SET_BIT(FIBRE);
SET_BIT(1000baseT_Full);
SET_BIT(1000baseX_Full);
SET_BIT(10000baseCR_Full);
SET_BIT(10000baseLR_Full);
SET_BIT(10000baseSR_Full);
SET_BIT(40000baseCR4_Full);
SET_BIT(40000baseSR4_Full);
SET_BIT(100000baseCR4_Full);
SET_BIT(100000baseSR4_Full);
SET_BIT(25000baseCR_Full);
SET_BIT(25000baseSR_Full);
SET_BIT(50000baseCR2_Full);
SET_BIT(TP);
SET_BIT(10baseT_Half);
SET_BIT(10baseT_Full);
SET_BIT(100baseT_Half);
SET_BIT(100baseT_Full);
SET_BIT(1000baseT_Half);
SET_BIT(1000baseT_Full);
SET_BIT(10000baseT_Full);
SET_BIT(Pause);
SET_BIT(Asym_Pause);
SET_BIT(Autoneg);
case SET_BIT:
S24C16_set_bit(np, 1, gpreg, SET_BIT);
S24C16_set_bit(np, 1, gpreg, SET_BIT);
S24C16_set_bit(np, write_bit, gpreg, SET_BIT);
SET_BIT(value, 2);
SET_BIT(value, 7);
SET_BIT(value, 2);
SET_BIT(value, 2);
SET_BIT(value, 0);
SET_BIT(value, 2);
SET_BIT(value, 0);
SET_BIT(value, 7);
SET_BIT(value, 2);
tmp |= SET_BIT(14);
tmp |= SET_BIT(14);
tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
tmp |= SET_BIT(31); /* Overlay format to Planer */
tmp |= SET_BIT(7);
tmp |= SET_BIT(1); /* video stream */
tmp &= ~SET_BIT(31);
tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
tmp |= SET_BIT(8);
tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31));