drivers/crypto/hisilicon/sec2/sec_main.c

1139

val = readl(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1140

writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1141

writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

479

reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

487

writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

608

val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

610

writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

626

val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

628

writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

649

reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

651

writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

726

val1 = readl(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

738

writel(val1, qm->io_base + SEC_CONTROL_REG);