SCTLR_ELx_M
u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C;
val &= (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | SCTLR_ELx_SA |
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
:: "r"(sctlr & ~SCTLR_ELx_M), "r"(ttbr), "r"(tcr), "r"(sctlr));
if (!(sctlr & SCTLR_ELx_M))
write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
cxt->sctlr = SCTLR_ELx_M;
if (!(cxt->sctlr & SCTLR_ELx_M)) {
if (!(val & SCTLR_ELx_M)) {
val |= SCTLR_ELx_M;
val |= SCTLR_ELx_M;
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I;