SCL
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, false);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, false);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, false);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, false);
write_bit_to_ddc(ddc_handle, SCL, false);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, true);
write_bit_to_ddc(ddc_handle, SCL, false);
if (read_bit_from_ddc(ddc, SCL))
SRI(SCL_TAP_CONTROL, SCL, id), \
SRI(SCL_CONTROL, SCL, id), \
SRI(SCL_BYPASS_CONTROL, SCL, id), \
SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
SRI(SCL_COEF_RAM_SELECT, SCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
SRI(VIEWPORT_START, SCL, id), \
SRI(VIEWPORT_SIZE, SCL, id), \
SRI(SCL_SCALER_ENABLE, SCL, id), \
SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \
SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_VERT_FILTER_INIT, SCL, id), \
SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
SRI(SCL_UPDATE, SCL, id), \
SRI(SCL_F_SHARP_CONTROL, SCL, id)
SRI(SCL_MODE, SCL, id), \
SRI(SCL_TAP_CONTROL, SCL, id), \
SRI(SCL_CONTROL, SCL, id), \
SRI(SCL_BYPASS_CONTROL, SCL, id), \
SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
SRI(SCL_COEF_RAM_SELECT, SCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
SRI(VIEWPORT_START, SCL, id), \
SRI(VIEWPORT_SIZE, SCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
SRI(SCL_VERT_FILTER_INIT, SCL, id), \
SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
SRI(SCL_UPDATE, SCL, id), \
SRI(SCL_F_SHARP_CONTROL, SCL, id)
DDC_I2C_REG_LIST(SCL)\
DDC_REG_LIST_DCN2(SCL)\
u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA);
ones |= SCL;
ones &= ~SCL;
u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA);
return (ioc_readb(IOC_CONTROL) & SCL) != 0;
force_ones = FORCE_ONES | SCL | SDA;
writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC));
return !!(readl(i2c->base + I2C_CONTROL) & SCL);
writel(SCL | SDA, i2c->base + I2C_CONTROLS);
scsptr1_data &= ~SCL; /* SCL:L */
scsptr1_data |= SCL; /* SCL:H */
scsptr1_data &= ~SCL; /* SCL:L */
scsptr1_data |= SCL; /* SCL:H */
scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
nsp32_prom_set(data, SCL, 1);
nsp32_prom_set(data, SCL, 0);
nsp32_prom_set(data, SCL, 1);
nsp32_prom_set(data, SCL, 0);
nsp32_prom_set(data, SCL, 1 );
nsp32_prom_set(data, SCL, 0 );
nsp32_prom_set(data, SCL, 1);
nsp32_prom_set(data, SCL, 0);