RxComplete
outw(SetIntrEnb | IntLatch|TxAvailable|TxComplete|RxComplete|StatsFull,
(IntLatch | RxComplete | StatsFull)) {
if (status & RxComplete)
if (status & RxComplete)
RxComplete | AdapterFailure |
} while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
(vp->full_bus_master_rx ? UpComplete : RxComplete) |
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
(IntLatch | RxComplete | RxEarly | StatsFull)) {
if (status & RxComplete)
outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
(IntLatch | RxComplete | StatsFull)) {
if (status & RxComplete)
(vp->full_bus_master_rx ? UpComplete : RxComplete) |
(vp->full_bus_master_rx ? 0 : RxComplete) |
if (status & RxComplete)
} while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));