arch/arm64/include/asm/insn.h

670

enum aarch64_insn_register Rm,

arch/arm64/kvm/pauth.c

29

: [Rn] "r" ((n)), [Rm] "r" ((m)))

arch/arm64/lib/insn.c

1471

enum aarch64_insn_register Rm,

arch/arm64/lib/insn.c

1499

return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);

arch/arm64/net/bpf_jit.h

232

#define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \

arch/arm64/net/bpf_jit.h

233

aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \

arch/arm64/net/bpf_jit.h

236

#define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)

arch/arm64/net/bpf_jit.h

237

#define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)

arch/arm64/net/bpf_jit.h

238

#define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)

arch/arm64/net/bpf_jit.h

240

#define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)

arch/arm64/net/bpf_jit.h

242

#define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)

arch/arm64/net/bpf_jit.h

254

#define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \

arch/arm64/net/bpf_jit.h

256

#define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)

arch/arm64/net/bpf_jit.h

257

#define A64_SDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, SDIV)

arch/arm64/net/bpf_jit.h

258

#define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)

arch/arm64/net/bpf_jit.h

259

#define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)

arch/arm64/net/bpf_jit.h

260

#define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)

arch/arm64/net/bpf_jit.h

264

#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \

arch/arm64/net/bpf_jit.h

267

#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \

arch/arm64/net/bpf_jit.h

270

#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)

arch/arm64/net/bpf_jit.h

273

#define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \

arch/arm64/net/bpf_jit.h

274

aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \

arch/arm64/net/bpf_jit.h

277

#define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)

arch/arm64/net/bpf_jit.h

278

#define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)

arch/arm64/net/bpf_jit.h

279

#define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)

arch/arm64/net/bpf_jit.h

280

#define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)

arch/arm64/net/bpf_jit.h

282

#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)

arch/arm64/net/bpf_jit.h

284

#define A64_MVN(sf, Rd, Rm) \

arch/arm64/net/bpf_jit.h

285

A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)

arch/arm64/net/bpf_jit.h

56

#define A64_LS_REG(Rt, Rn, Rm, size, type) \

arch/arm64/net/bpf_jit.h

57

aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \

arch/sh/math-emu/math.c

162

MREAD(FRn, Rm + R0 + 4);

arch/sh/math-emu/math.c

164

MREAD(FRn, Rm + R0);

arch/sh/math-emu/math.c

166

MREAD(FRn, Rm + R0);

arch/sh/math-emu/math.c

178

MREAD(FRn, Rm + 4);

arch/sh/math-emu/math.c

180

MREAD(FRn, Rm);

arch/sh/math-emu/math.c

182

MREAD(FRn, Rm);

arch/sh/math-emu/math.c

194

MREAD(FRn, Rm + 4);

arch/sh/math-emu/math.c

196

MREAD(FRn, Rm);

arch/sh/math-emu/math.c

197

Rm += 8;

arch/sh/math-emu/math.c

199

MREAD(FRn, Rm);

arch/sh/math-emu/math.c

200

Rm += 4;