arch/mips/include/asm/mips-boards/bonito64.h

411

#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)

arch/mips/kernel/traps.c

546

((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);

arch/mips/kernel/traps.c

586

((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);

arch/mips/kernel/traps.c

717

#define RS BASE

arch/sparc/net/bpf_jit_comp_32.c

181

#define emit_loadptr(BASE, STRUCT, FIELD, DEST) \

arch/sparc/net/bpf_jit_comp_32.c

184

*prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \

arch/sparc/net/bpf_jit_comp_32.c

187

#define emit_load32(BASE, STRUCT, FIELD, DEST) \

arch/sparc/net/bpf_jit_comp_32.c

190

*prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \

arch/sparc/net/bpf_jit_comp_32.c

193

#define emit_load16(BASE, STRUCT, FIELD, DEST) \

arch/sparc/net/bpf_jit_comp_32.c

196

*prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \

arch/sparc/net/bpf_jit_comp_32.c

199

#define __emit_load8(BASE, STRUCT, FIELD, DEST) \

arch/sparc/net/bpf_jit_comp_32.c

201

*prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \

arch/sparc/net/bpf_jit_comp_32.c

204

#define emit_load8(BASE, STRUCT, FIELD, DEST) \

arch/sparc/net/bpf_jit_comp_32.c

206

__emit_load8(BASE, STRUCT, FIELD, DEST); \

arch/sparc/net/bpf_jit_comp_32.c

237

#define emit_jmpl(BASE, IMM_OFF, LREG) \

arch/sparc/net/bpf_jit_comp_32.c

238

*prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

54

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

50

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

60

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

96

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

104

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

135

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

54

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

46

.reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

35

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

39

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

44

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

61

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

64

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

52

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

55

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

58

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

61

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

52

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

55

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

60

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

66

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

56

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

58

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

64

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

56

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

67

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

73

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

61

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

64

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

70

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

56

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

60

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

66

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

54

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

40

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

46

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

29

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

72

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

169

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

172

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

122

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

179

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

183

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

186

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

190

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

171

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

175

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

117

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

174

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

178

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

176

(BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

180

(BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

181

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

185

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

185

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

189

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

173

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

177

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

152

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

156

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

151

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

155

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

165

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

169

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

39

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

138

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

142

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

785

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

114

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

118

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

123

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

127

.reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

834

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1014

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

130

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

134

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

138

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

147

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

151

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

155

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

159

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

253

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

257

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

261

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

265

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

272

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

276

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

871

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

103

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

107

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1109

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

111

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

115

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

119

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

123

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

119

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

123

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

127

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

131

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

135

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

139

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

143

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

150

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

154

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

994

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

118

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

122

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

126

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

130

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

134

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

138

.reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

143

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

147

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

154

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

158

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

965

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

181

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

187

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

190

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

193

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

197

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

201

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

205

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

212

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

964

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

177

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

183

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

186

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

189

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

193

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

197

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

201

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

208

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

909

generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1182

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

130

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

134

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

138

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

142

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

146

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

150

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

154

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

161

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

165

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

674

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1240

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

151

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

155

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

159

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

163

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

167

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

171

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

178

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

182

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

681

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1181

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

164

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

168

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

172

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

176

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

180

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

184

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

188

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

195

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

199

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

673

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1174

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

150

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

154

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

158

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

162

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

166

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

170

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

174

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

181

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

185

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

668

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

154

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

166

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

177

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

527

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

154

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

166

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

174

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

523

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1190

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

133

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

143

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

147

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

151

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

154

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

158

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

162

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

166

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

170

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

174

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

178

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

182

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

186

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

193

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

197

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

549

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

113

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

117

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1170

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

123

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

127

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

131

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

134

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

138

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

142

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

146

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

150

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

154

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

158

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

162

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

166

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

173

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

177

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

529

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1177

generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

118

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

151

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

155

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

159

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

163

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

167

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

171

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

178

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

182

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

536

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

100

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

103

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

109

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

113

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

120

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

123

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

126

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

130

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

134

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

141

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

145

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

149

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

153

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

157

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

161

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

168

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

502

.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

37

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

38

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

38

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

14

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

14

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

17

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

37

#define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name)

drivers/gpu/drm/nouveau/dispnv50/base907c.c

180

NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) |

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h

326

#define VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL,BASE,SIZE,NEXT) do { \

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h

330

u64 _addr = ((BASE) + MAP->off); \

drivers/hwmon/pc87360.c

1654

val = (superio_inb(sioaddr, BASE) << 8)

drivers/hwmon/pc87360.c

1655

| superio_inb(sioaddr, BASE + 1);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

1025

writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

459

writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

483

writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));

drivers/media/pci/cobalt/cobalt-omnitek.c

43

#define CAPABILITY_HEADER (BASE)

drivers/media/pci/cobalt/cobalt-omnitek.c

44

#define CAPABILITY_REGISTER (BASE + 0x04)

drivers/media/pci/cobalt/cobalt-omnitek.c

47

#define INTERRUPT_STATUS (BASE + 0x08)

drivers/media/pci/cobalt/cobalt-omnitek.c

48

#define PCI(c) (BASE + 0x40 + ((c) * 0x40))

drivers/media/pci/cobalt/cobalt-omnitek.c

49

#define SIZE(c) (BASE + 0x58 + ((c) * 0x40))

drivers/media/pci/cobalt/cobalt-omnitek.c

50

#define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40))

drivers/media/pci/cobalt/cobalt-omnitek.c

51

#define CS_REG(c) (BASE + 0x60 + ((c) * 0x40))

drivers/media/pci/cobalt/cobalt-omnitek.c

52

#define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40))

drivers/media/tuners/xc2028-types.h

15

#define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1)

drivers/media/tuners/xc2028.c

178

if (type & BASE)

drivers/media/tuners/xc2028.c

453

if (type & BASE)

drivers/media/tuners/xc2028.c

762

(((BASE | new_fw.type) & BASE_TYPES) ==

drivers/media/tuners/xc2028.c

778

rc = load_firmware(fe, BASE | new_fw.type, &std0);

drivers/media/tuners/xc2028.c

788

rc = load_firmware(fe, BASE | INIT1 | new_fw.type, &std0);

drivers/media/tuners/xc2028.c

790

rc = load_firmware(fe, (BASE | INIT1 | new_fw.type) & ~F8MHZ,

drivers/media/tuners/xc2028.c

803

if (priv->cur_fw.type == (BASE | new_fw.type) &&

drivers/media/tuners/xc2028.c

880

priv->cur_fw.type |= BASE;

drivers/media/tuners/xc4000.c

1070

priv->cur_fw.type |= BASE;

drivers/media/tuners/xc4000.c

1523

& (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) {

drivers/media/tuners/xc4000.c

1556

if (priv->cur_fw.type & BASE)

drivers/media/tuners/xc4000.c

1583

(priv->cur_fw.type & BASE) != 0) {

drivers/media/tuners/xc4000.c

1697

id = ((priv->cur_fw.type & BASE) != 0 ?

drivers/media/tuners/xc4000.c

552

if (type & BASE)

drivers/media/tuners/xc4000.c

641

& (BASE | INIT1 | FM | DTV6 | DTV7 | DTV78 | DTV8 | SCODE))

drivers/media/tuners/xc4000.c

960

if (priv->cur_fw.type & BASE) {

drivers/media/tuners/xc4000.c

975

rc = load_firmware(fe, BASE, &std0);

drivers/media/tuners/xc4000.c

984

rc = load_firmware(fe, BASE | INIT1, &std0);

drivers/media/tuners/xc4000.c

986

rc = load_firmware(fe, BASE | INIT1, &std0);

drivers/media/tuners/xc4000.c

998

if (priv->cur_fw.type == (BASE | new_fw.type) &&

drivers/net/ethernet/smsc/smc9194.c

886

base_address_register = inw( ioaddr + BASE );

drivers/ps3/ps3av_cmd.c

493

[PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 },

drivers/ps3/ps3av_cmd.c

494

[PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 },

drivers/ps3/ps3av_cmd.c

495

[PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 },

drivers/ps3/ps3av_cmd.c

496

[PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 },

drivers/ps3/ps3av_cmd.c

497

[PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 },

drivers/ps3/ps3av_cmd.c

498

[PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 }

drivers/ps3/ps3av_cmd.c

540

ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d];

fs/xfs/libxfs/xfs_da_btree.h

165

#define XFS_DA_LOGOFF(BASE, ADDR) ((char *)(ADDR) - (char *)(BASE))

fs/xfs/libxfs/xfs_da_btree.h

166

#define XFS_DA_LOGRANGE(BASE, ADDR, SIZE) \

fs/xfs/libxfs/xfs_da_btree.h

167

(uint)(XFS_DA_LOGOFF(BASE, ADDR)), \

fs/xfs/libxfs/xfs_da_btree.h

168

(uint)(XFS_DA_LOGOFF(BASE, ADDR)+(SIZE)-1)

include/linux/zutil.h

100

s1 %= BASE;

include/linux/zutil.h

101

s2 %= BASE;

sound/soc/qcom/lpass-lpaif-reg.h

163

__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \

sound/soc/qcom/lpass-lpaif-reg.h

164

__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))

tools/testing/selftests/bpf/test_sockmap.c

1055

if (test == BASE || test == BASE_SENDPAGE)

tools/testing/selftests/bpf/test_sockmap.c

1364

} else if (test == BASE) {

tools/testing/selftests/bpf/test_sockmap.c

2174

test = BASE;

tools/testing/selftests/kvm/riscv/get-reg-list.c

1148

KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);