RX_QUEUE_SIZE
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
s += RX_QUEUE_SIZE;
rxq->write = (rxq->write + 1) % RX_QUEUE_SIZE;
for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
if (ipw_rx_queue_space (priv->rxq) > (RX_QUEUE_SIZE / 2))
i = (i + 1) % RX_QUEUE_SIZE;
struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
total_empty += RX_QUEUE_SIZE;
if (total_empty > (RX_QUEUE_SIZE / 2))
il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
for (i = 0; i < RX_QUEUE_SIZE; i++)
for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
total_empty += RX_QUEUE_SIZE;
if (total_empty > (RX_QUEUE_SIZE / 2))
il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
s += RX_QUEUE_SIZE;
rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
struct il_rx_buf *queue[RX_QUEUE_SIZE];
struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
for (i = 0; i < RX_QUEUE_SIZE; i++)
trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE;
rxq->queue_size = RX_QUEUE_SIZE;
trans_pcie->num_rx_bufs = RX_QUEUE_SIZE;