drivers/gpu/drm/i915/gt/intel_engine_cs.c

1628

const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1695

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1856

!(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2101

ENGINE_READ(engine, RING_MI_MODE),

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2102

ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

1977

ENGINE_READ(engine, RING_MI_MODE));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2942

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1097

(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

124

if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)

drivers/gpu/drm/i915/gt/intel_ring_submission.c

277

RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

278

ENGINE_POSTING_READ(engine, RING_MI_MODE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2607

RING_MI_MODE(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2663

wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

368

wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

890

wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);

drivers/gpu/drm/i915/gt/selftest_lrc.c

325

i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

71

{ RING_MI_MODE(0), 0, 0, "MODE" }, \

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

4419

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

4420

ENGINE_POSTING_READ(engine, RING_MI_MODE);

drivers/gpu/drm/i915/gvt/handlers.c

2261

MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/mmio_context.c

140

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

drivers/gpu/drm/i915/gvt/mmio_context.c

86

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

drivers/gpu/drm/i915/i915_gpu_error.c

1354

ee->mode = ENGINE_READ(engine, RING_MI_MODE);

drivers/gpu/drm/i915/i915_pmu.c

386

val = ENGINE_READ_FW(engine, RING_MI_MODE);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

105

MMIO_RING_D(RING_MI_MODE);

drivers/gpu/drm/i915/intel_uncore.c

1761

__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);

drivers/gpu/drm/xe/xe_guc_capture.c

113

{ RING_MI_MODE(0), REG_32BIT, 0, 0, 0, "RING_MI_MODE"}, \

drivers/gpu/drm/xe/xe_hw_engine.c

343

xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0),

drivers/gpu/drm/xe/xe_hw_engine.c

345

xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));