drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2945

RING_HWS_PGA,

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2947

ENGINE_POSTING_READ(engine, RING_HWS_PGA);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

111

hwsp = RING_HWS_PGA(engine->mmio_base);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

392

ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

73

{ RING_HWS_PGA(0), 0, 0, "HWS" }, \

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

4409

RING_HWS_PGA,

drivers/gpu/drm/i915/gvt/handlers.c

2568

MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);

drivers/gpu/drm/i915/i915_gpu_error.c

1381

mmio = RING_HWS_PGA(engine->mmio_base);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

831

MMIO_RING_D(RING_HWS_PGA);

drivers/gpu/drm/xe/xe_execlist.c

81

xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

83

xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));

drivers/gpu/drm/xe/xe_guc_ads.c

746

{ .reg = RING_HWS_PGA(hwe->mmio_base), },

drivers/gpu/drm/xe/xe_guc_capture.c

109

{ RING_HWS_PGA(0), REG_32BIT, 0, 0, 0, "RING_HWS_PGA"}, \

drivers/gpu/drm/xe/xe_hw_engine.c

337

xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),