Symbol: REG_SET_2
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
64
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
88
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
72
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
365
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
371
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1128
REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1145
REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1297
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1879
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1885
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2492
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
95
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
248
value = REG_SET_2(AUX_SW_DATA, value,
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
232
value = REG_SET_2(DC_I2C_DATA, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
240
REG_SET_2(DC_I2C_DATA, value,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
118
REG_SET_2(CUR_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
148
REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
152
REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
156
REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
243
REG_SET_2(DEGAMMA_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
56
REG_SET_2(CUR_POSITION, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
60
REG_SET_2(CUR_HOT_SPOT, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
233
REG_SET_2(DP_DPHY_SYM2, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
172
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
187
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
202
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
206
REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
577
REG_SET_2(GRPH_SWAP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
827
REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
367
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
375
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
380
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
385
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
391
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
396
REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
400
REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
404
REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
427
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
435
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
440
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
445
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
451
REG_SET_2(FMT_CLAMP_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
464
REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
489
REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
506
REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
726
REG_SET_2(DP_MSE_RATE_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1091
REG_SET_2(GAMUT_REMAP_C11_C12, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1094
REG_SET_2(GAMUT_REMAP_C13_C14, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1097
REG_SET_2(GAMUT_REMAP_C21_C22, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1100
REG_SET_2(GAMUT_REMAP_C23_C24, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1103
REG_SET_2(GAMUT_REMAP_C31_C32, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1106
REG_SET_2(GAMUT_REMAP_C33_C34, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1254
REG_SET_2(OUTPUT_CSC_C11_C12, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1259
REG_SET_2(OUTPUT_CSC_C13_C14, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1264
REG_SET_2(OUTPUT_CSC_C21_C22, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1269
REG_SET_2(OUTPUT_CSC_C23_C24, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1274
REG_SET_2(OUTPUT_CSC_C31_C32, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1279
REG_SET_2(OUTPUT_CSC_C33_C34, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
139
REG_SET_2(SCL_TAP_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1500
REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1510
REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
175
REG_SET_2(SCL_TAP_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
210
REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
213
REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
277
REG_SET_2(VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
281
REG_SET_2(VIEWPORT_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
362
REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
366
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
386
REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
391
REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
395
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
430
REG_SET_2(LB_MEMORY_CTRL, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
627
REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
631
REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
635
REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
112
REG_SET_2(reg->start_end_cntl2_b, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
118
REG_SET_2(reg->start_end_cntl2_g, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
124
REG_SET_2(reg->start_end_cntl2_r, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
56
REG_SET_2(cur_csc_reg, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
93
REG_SET_2(reg->start_cntl_b, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
96
REG_SET_2(reg->start_cntl_g, 0,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
99
REG_SET_2(reg->start_cntl_r, 0,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
88
REG_SET_2(CNTL, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
51
REG_SET_2(reg->start_cntl_b, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
54
REG_SET_2(reg->start_cntl_g, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
57
REG_SET_2(reg->start_cntl_r, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
75
REG_SET_2(reg->start_end_cntl2_b, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
78
REG_SET_2(reg->start_end_cntl2_g, 0,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
81
REG_SET_2(reg->start_end_cntl2_r, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
162
REG_SET_2(DP_DPHY_SYM2, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
419
REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
443
REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
458
REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
646
REG_SET_2(DP_MSE_RATE_CNTL, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
175
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
185
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
195
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
205
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
226
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
236
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
246
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
256
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
266
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
276
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
286
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
291
REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
661
REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
685
REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
700
REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
568
REG_SET_2(CM_BNS_VALUES_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
572
REG_SET_2(CM_BNS_VALUES_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
576
REG_SET_2(CM_BNS_VALUES_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
202
REG_SET_2(LB_DATA_FORMAT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
210
REG_SET_2(LB_MEMORY_CTRL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
368
REG_SET_2(SCL_MODE, scl_mode,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
533
REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
539
REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
545
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
554
REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
561
REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
570
REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
590
REG_SET_2(RECOUT_START, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
596
REG_SET_2(RECOUT_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
649
REG_SET_2(MPC_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
674
REG_SET_2(SCL_BLACK_OFFSET, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
679
REG_SET_2(SCL_BLACK_OFFSET, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
118
REG_SET_2(FORMAT_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1066
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1070
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1074
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
637
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
640
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
643
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
647
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
651
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
655
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
787
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
790
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
793
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
797
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
801
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
805
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
60
REG_SET_2(FORMAT_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1081
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1084
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1087
REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1091
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1095
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1099
REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1365
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1369
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1373
REG_SET_2(CM_3DLUT_DATA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
215
REG_SET_2(PRE_DEGAM, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
241
REG_SET_2(FORMAT_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
360
REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
365
REG_SET_2(PRE_DEALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
368
REG_SET_2(PRE_REALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
931
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
934
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
937
REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
941
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
945
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
949
REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
155
REG_SET_2(CM_DEALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
167
REG_SET_2(CM_BIAS_Y_G_CB_B, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
190
REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
195
REG_SET_2(PRE_DEALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
198
REG_SET_2(PRE_REALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
75
REG_SET_2(FORMAT_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1017
REG_SET_2(ISHARP_LBA_PWL_SEG5, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1141
REG_SET_2(MPC_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1170
REG_SET_2(SCL_BLACK_OFFSET, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1175
REG_SET_2(SCL_BLACK_OFFSET, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
200
REG_SET_2(LB_DATA_FORMAT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
208
REG_SET_2(LB_MEMORY_CTRL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
378
REG_SET_2(SCL_MODE, scl_mode,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
540
REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
544
REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
548
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
553
REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
558
REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
563
REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
586
REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
592
REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
598
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
607
REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
614
REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
623
REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
643
REG_SET_2(RECOUT_START, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
649
REG_SET_2(RECOUT_SIZE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
689
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL1, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
692
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL2, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
695
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL3, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
699
REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
703
REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
741
REG_SET_2(DSCL_EASF_V_BF1_PWL_SEG7, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
765
REG_SET_2(DSCL_EASF_V_BF3_PWL_SEG5, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
804
REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
808
REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
846
REG_SET_2(DSCL_EASF_H_BF1_PWL_SEG7, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
870
REG_SET_2(DSCL_EASF_H_BF3_PWL_SEG5, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
890
REG_SET_2(DSCL_SC_MODE, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
894
REG_SET_2(DSCL_SC_MATRIX_C0C1, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
897
REG_SET_2(DSCL_SC_MATRIX_C2C3, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
986
REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
138
REG_SET_2(FORMAT_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
253
REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
258
REG_SET_2(PRE_DEALPHA, 0,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
261
REG_SET_2(PRE_REALPHA, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
603
REG_SET_2(DSCCIF_CONFIG1, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
652
REG_SET_2(DSCC_PPS_CONFIG2, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
656
REG_SET_2(DSCC_PPS_CONFIG3, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
663
REG_SET_2(DSCC_PPS_CONFIG5, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
672
REG_SET_2(DSCC_PPS_CONFIG7, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
676
REG_SET_2(DSCC_PPS_CONFIG8, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
680
REG_SET_2(DSCC_PPS_CONFIG9, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
215
REG_SET_2(DSCCIF_CONFIG0, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
271
REG_SET_2(DSCC_PPS_CONFIG2, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
275
REG_SET_2(DSCC_PPS_CONFIG3, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
282
REG_SET_2(DSCC_PPS_CONFIG5, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
291
REG_SET_2(DSCC_PPS_CONFIG7, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
295
REG_SET_2(DSCC_PPS_CONFIG8, 0,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
299
REG_SET_2(DSCC_PPS_CONFIG9, 0,
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
101
REG_SET_2(gpio.MASK_reg, regval,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
266
REG_SET_2(HDMI_TB_ENC_H_ACTIVE_BLANK, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
277
REG_SET_2(HDMI_TB_ENC_HC_ACTIVE_BLANK, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
571
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
581
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
591
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
601
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
611
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
621
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
631
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
636
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
406
REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
411
REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
416
REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
421
REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL3, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
278
REG_SET_2(HDMI_TB_ENC_H_ACTIVE_BLANK, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
287
REG_SET_2(HDMI_TB_ENC_HC_ACTIVE_BLANK, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
608
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
618
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
628
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
638
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
648
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
658
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
668
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, 0,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
673
REG_SET_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
157
REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
202
REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
247
REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
292
REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
353
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
370
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
388
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
405
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
423
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
440
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
458
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
475
REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
507
REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
525
REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
543
REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
561
REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
386
REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
70
REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
70
REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
68
REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1193
REG_SET_2(CURSOR_SETTINS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1280
REG_SET_2(CURSOR_POSITION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1284
REG_SET_2(CURSOR_HOT_SPOT, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
617
REG_SET_2(BLANK_OFFSET_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
627
REG_SET_2(DST_AFTER_SCALER, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
652
REG_SET_2(PER_LINE_DELIVERY, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
674
REG_SET_2(DCN_TTU_QOS_WM, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
719
REG_SET_2(PREFETCH_SETTINS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
726
REG_SET_2(VBLANK_PARAMETERS_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
736
REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
749
REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
797
REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
837
REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
844
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
856
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
860
REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
865
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
869
REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
874
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
878
REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
882
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
886
REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1076
REG_SET_2(CURSOR_POSITION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1080
REG_SET_2(CURSOR_HOT_SPOT, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
124
REG_SET_2(PER_LINE_DELIVERY, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
146
REG_SET_2(DCN_TTU_QOS_WM, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
253
REG_SET_2(PREFETCH_SETTINGS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
260
REG_SET_2(VBLANK_PARAMETERS_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
264
REG_SET_2(FLIP_PARAMETERS_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
277
REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
292
REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
634
REG_SET_2(CURSOR_SETTINGS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
76
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
89
REG_SET_2(BLANK_OFFSET_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
99
REG_SET_2(DST_AFTER_SCALER, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
193
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
197
REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
202
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
206
REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
211
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
215
REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
219
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
223
REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
246
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
63
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
159
REG_SET_2(CURSOR_SETTINGS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
259
REG_SET_2(BLANK_OFFSET_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
269
REG_SET_2(DST_AFTER_SCALER, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
294
REG_SET_2(PER_LINE_DELIVERY, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
316
REG_SET_2(DCN_TTU_QOS_WM, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
366
REG_SET_2(PREFETCH_SETTINGS, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
373
REG_SET_2(VBLANK_PARAMETERS_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
377
REG_SET_2(FLIP_PARAMETERS_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
390
REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
403
REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
658
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
662
REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
667
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
671
REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
676
REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
680
REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
684
REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
688
REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
709
REG_SET_2(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
794
REG_SET_2(CURSOR_POSITION, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
798
REG_SET_2(CURSOR_HOT_SPOT, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
161
REG_SET_2(BLANK_OFFSET_0, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
171
REG_SET_2(DST_AFTER_SCALER, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
196
REG_SET_2(PER_LINE_DELIVERY, 0,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
218
REG_SET_2(DCN_TTU_QOS_WM, 0,
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
71
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
76
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
677
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
87
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
816
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
93
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
174
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
94
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1013
REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1017
REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1021
REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
494
REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
497
REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
500
REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
504
REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
507
REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
510
REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
643
REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
646
REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
649
REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
653
REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
656
REG_SET_2(SHAPER_RAMB_END_CNTL_G[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
659
REG_SET_2(SHAPER_RAMB_END_CNTL_R[rmu_idx], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
351
REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
354
REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
357
REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
361
REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
364
REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
367
REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
503
REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
506
REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
509
REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
513
REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
516
REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
519
REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
843
REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
847
REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
851
REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
274
REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
277
REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
280
REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
284
REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
287
REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
290
REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
426
REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
429
REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
432
REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
436
REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
439
REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
442
REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
172
REG_SET_2(DPG_COLOUR_R_CR, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
175
REG_SET_2(DPG_COLOUR_G_Y, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
178
REG_SET_2(DPG_COLOUR_B_CB, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
283
REG_SET_2(DPG_DIMENSIONS, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
300
REG_SET_2(DPG_DIMENSIONS, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
313
REG_SET_2(DPG_COLOUR_B_CB, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
316
REG_SET_2(DPG_COLOUR_G_Y, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
319
REG_SET_2(DPG_COLOUR_R_CR, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
93
REG_SET_2(DPG_DIMENSIONS, 0,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
98
REG_SET_2(DPG_OFFSET_SEGMENT, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
102
REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1119
REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1131
REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
114
REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
87
REG_SET_2(OTG_VUPDATE_PARAM, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
886
REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
492
REG_SET_2(OTG_CRC_CNTL2, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
163
REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
430
REG_SET_2(OTG_VUPDATE_PARAM, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
172
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
181
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
210
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
225
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
237
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
243
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
254
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
260
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
270
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
105
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
114
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
141
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
156
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
167
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
173
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
184
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
190
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
200
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
173
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
182
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
207
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
216
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
225
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
231
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
241
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
183
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
192
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
215
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
224
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
249
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
258
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
267
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
273
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
283
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
176
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
185
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
204
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
211
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
233
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
242
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
251
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
257
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
267
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
275
REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
157
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
166
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
190
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
199
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
224
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
233
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
242
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
248
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
258
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
266
REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
183
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
192
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
211
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
218
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
240
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
249
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
258
REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
264
REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
274
REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
282
REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,