drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c

461

REG_GET_4(DP_PIXEL_FORMAT,

drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c

115

REG_GET_4(HDMI_FRL_ENC_CONFIG,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

521

REG_GET_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

904

REG_GET_4(DCN_EXPANSION_MODE,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1151

REG_GET_4(DCN_EXPANSION_MODE,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1384

REG_GET_4(DCN_EXPANSION_MODE,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

267

REG_GET_4(DCN_EXPANSION_MODE,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

837

REG_GET_4(DCN_EXPANSION_MODE,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

661

REG_GET_4(HUBP_3DLUT_CONTROL,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

60

val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

450

REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

551

REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1482

REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

1015

REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_SHAPER_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_shaper_mem_pwr_force,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

989

REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_3DLUT_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_force,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

998

REG_GET_4(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_inst], MPC_RMCM_3DLUT_READ_SEL, &s->rmcm_regs.rmcm_3dlut_read_sel,