Symbol: REG_GET_2
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
85
REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
73
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
78
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
83
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
88
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
73
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
78
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
83
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
88
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1355
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1360
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1365
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1370
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2211
REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0],
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2214
REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1],
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2217
REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2],
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2220
REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3],
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2223
REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, &fe_clk_en[4],
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
653
REG_GET_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, &src_sel, SYMCLK32_SE3_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
880
REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, &src_sel, SYMCLKA_FE_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
883
REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, &src_sel, SYMCLKB_FE_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
886
REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, &src_sel, SYMCLKC_FE_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
889
REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, &src_sel, SYMCLKD_FE_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
892
REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, &src_sel, SYMCLKE_FE_EN, &en);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
976
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
981
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
986
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
991
REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
131
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
136
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
141
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
146
REG_GET_2(OTG_PIXEL_RATE_DIV,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
497
REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
569
REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
272
REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
152
REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
168
REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
205
REG_GET_2(BL_PWM_PERIOD_CNTL,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
74
REG_GET_2(cur_csc_reg,
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
59
REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
175
REG_GET_2(PWRSEQ_CNTL, PANEL_DIGON, &dig_on, PANEL_DIGON_OVRD, &dig_on_ovrd);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1525
REG_GET_2(DP_PIXEL_FORMAT,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
66
REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
976
REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
53
REG_GET_2(PRE_DEGAM,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
155
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
238
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
97
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
108
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
155
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
153
REG_GET_2(DWB_OGAM_CONTROL,
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
113
REG_GET_2(gpio.MASK_reg,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
232
REG_GET_2(HDMI_FRL_ENC_CONFIG,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
937
REG_GET_2(HDMI_TB_ENC_PIXEL_FORMAT,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
944
REG_GET_2(HDMI_TB_ENC_H_ACTIVE_BLANK,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
467
REG_GET_2(DP_DPHY_SYM32_SAT_VC0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
470
REG_GET_2(DP_DPHY_SYM32_SAT_VC1,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
473
REG_GET_2(DP_DPHY_SYM32_SAT_VC2,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
476
REG_GET_2(DP_DPHY_SYM32_SAT_VC3,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
480
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
483
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
486
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
489
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL3,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
159
REG_GET_2(HDMI_TB_ENC_PIXEL_FORMAT,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
166
REG_GET_2(HDMI_TB_ENC_H_ACTIVE_BLANK,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
42
REG_GET_2(DP_DPHY_SYM32_SAT_VC0,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
45
REG_GET_2(DP_DPHY_SYM32_SAT_VC1,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
48
REG_GET_2(DP_DPHY_SYM32_SAT_VC2,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
52
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
55
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
58
REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2,
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
568
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
952
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
983
REG_GET_2(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, &mall_en,
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
268
REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1014
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1018
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1053
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1057
REG_GET_2(DCSURF_SURFACE_CONFIG,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1078
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
927
REG_GET_2(BLANK_OFFSET_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
937
REG_GET_2(DST_AFTER_SCALER,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
942
REG_GET_2(PREFETCH_SETTINS,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
946
REG_GET_2(PREFETCH_SETTINGS,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
950
REG_GET_2(VBLANK_PARAMETERS_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
978
REG_GET_2(PER_LINE_DELIVERY_PRE,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
982
REG_GET_2(PER_LINE_DELIVERY,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1164
REG_GET_2(BLANK_OFFSET_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1174
REG_GET_2(DST_AFTER_SCALER,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1179
REG_GET_2(PREFETCH_SETTINS,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1183
REG_GET_2(PREFETCH_SETTINGS,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1187
REG_GET_2(VBLANK_PARAMETERS_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1215
REG_GET_2(PER_LINE_DELIVERY_PRE,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1219
REG_GET_2(PER_LINE_DELIVERY,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1251
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1255
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1290
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1294
REG_GET_2(DCSURF_SURFACE_CONFIG,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1315
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1475
REG_GET_2(BLANK_OFFSET_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1482
REG_GET_2(DST_AFTER_SCALER,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1523
REG_GET_2(PER_LINE_DELIVERY,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1526
REG_GET_2(PER_LINE_DELIVERY_PRE,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1596
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
355
REG_GET_2(BLANK_OFFSET_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
362
REG_GET_2(DST_AFTER_SCALER,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
403
REG_GET_2(PER_LINE_DELIVERY,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
406
REG_GET_2(PER_LINE_DELIVERY_PRE,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
476
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1002
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
864
REG_GET_2(BLANK_OFFSET_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
874
REG_GET_2(DST_AFTER_SCALER,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
878
REG_GET_2(PREFETCH_SETTINGS,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
882
REG_GET_2(VBLANK_PARAMETERS_0,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
908
REG_GET_2(PER_LINE_DELIVERY_PRE,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
912
REG_GET_2(PER_LINE_DELIVERY,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
938
REG_GET_2(DCN_TTU_QOS_WM,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
942
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
977
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
981
REG_GET_2(DCSURF_SURFACE_CONFIG,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
676
REG_GET_2(_3DLUT_FL_BIAS_SCALE,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
679
REG_GET_2(_3DLUT_FL_CONFIG,
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
152
REG_GET_2(MPCC_STATUS[mpcc_id],
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
454
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
555
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
139
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1486
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1512
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
1007
REG_GET_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_inst], MPC_RMCM_3DLUT_OUT_OFFSET_R, &s->rmcm_regs.rmcm_3dlut_out_offset_r,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
1020
REG_GET_2(MPC_RMCM_SHAPER_CONTROL[mpcc_inst], MPC_RMCM_SHAPER_LUT_MODE, &s->rmcm_regs.rmcm_shaper_lut_mode,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
1023
REG_GET_2(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_inst], MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_shaper_lut_write_en_mask,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
1030
REG_GET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b,
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
1033
REG_GET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
330
REG_GET_2(DPG_CONTROL,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1242
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1343
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1365
REG_GET_2(OTG_V_SYNC_A,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1369
REG_GET_2(OTG_H_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1373
REG_GET_2(OTG_H_SYNC_A,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1420
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1424
REG_GET_2(OTG_H_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1579
REG_GET_2(OTG_CRC0_DATA_RG,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1589
REG_GET_2(OTG_CRC1_DATA_RG,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
476
REG_GET_2(OTG_BLANK_CONTROL,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
703
REG_GET_2(OTG_STATUS_POSITION,
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
314
REG_GET_2(OTG_PIPE_UPDATE_STATUS,
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
73
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
76
REG_GET_2(OTG_H_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
257
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
279
REG_GET_2(OTG_V_SYNC_A,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
283
REG_GET_2(OTG_H_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
287
REG_GET_2(OTG_H_SYNC_A,
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
248
REG_GET_2(OTG_CRC0_DATA_RG,
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
258
REG_GET_2(OTG_CRC1_DATA_RG,
drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
170
REG_GET_2(OTG_V_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
173
REG_GET_2(OTG_H_BLANK_START_END,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
455
REG_GET_2(CC_DC_HDMI_STRAPS,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
499
REG_GET_2(CC_DC_HDMI_STRAPS,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
479
REG_GET_2(CC_DC_HDMI_STRAPS,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
490
REG_GET_2(CC_DC_HDMI_STRAPS,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
496
REG_GET_2(CC_DC_HDMI_STRAPS,