RESET
writeb(RESET, RESET_PORT);
iowrite32(RESET, CR_AHB_RSTCR);
mhi_state(RESET, "RESET") \
ch_state_type(RESET, "RESET") \
ret = ph->xops->xfer_get_init(ph, RESET, sizeof(*dom), 0, &t);
temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0);
temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, RESET, 0);
dsi_write(dsi, DSI_PWR_UP, RESET);
dsi_write(dsi, DSI_PWR_UP, RESET);
dsi_write(dsi, DSI_PWR_UP, RESET);
regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
writel(RESET, base + PWR_UP);
SDVO_CMD_NAME_ENTRY(RESET),
ISKU_BIN_ATTR_W(reset, RESET);
if (state->state == RESET) {
state->state = RESET;
qt1070_write(client, RESET, 1);
if (ap.APSTAT1_a2.RESET || ap.APSTAT1_a2.IDLE || ap.APSTAT1_a2.STOP || hab.HABSTAT_a8.HABR) {
bcm3510_readB(st,0xa0,&v); v.HCTL1_a0.RESET = 1;
if (v.APSTAT1_a2.RESET)
if (!v.APSTAT1_a2.RESET)
u8 RESET :1;
u8 RESET :1;
return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
static u8 mt352_reset_attach [] = { RESET, 0xC0 };
zl10353_single_write(fe, RESET, 0x80);
return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
{ RESET, RESET_JPEG | RESET_DVP },
{ RESET, RESET_DVP },
{ RESET, 0x00}
{ RESET, 0x00 },
{ RESET, 0x00 },
{ RESET, 0x00 },
{ RESET, 0x00 },
static const u8 reset[] = { RESET, 0x80 };
static const u8 reset[] = { RESET, 0x80 };
static u8 reset [] = { RESET, 0x80 };
static u8 reset [] = { RESET, 0x80 };
static u8 reset [] = { RESET, 0x80 };
static u8 reset[] = { RESET, 0x80 };
static u8 reset[] = { RESET, 0x80 };
static u8 reset[] = { RESET, 0x80 };
static const u8 reset[] = { RESET, 0x80 };
static u8 reset[] = { RESET, 0x80 };
} else if (state == RESET)
/* RESET */ { RESET, IDLE },
tms = (wait_state == RESET) ? TMS_HIGH : TMS_LOW;
/* IRSELECT */ { RESET, IRCAPTURE },
case RESET:
case RESET:
case RESET:
case RESET:
XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
INIT_CMD(c, RESET, WRITE);
INIT_CMD(c, RESET, WRITE);
u32 RESET;
iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));
ath_dbg(ath9k_hw_common(ah), RESET,
ath_dbg(common, RESET, "Disabled BB Watchdog\n");
ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
ath_dbg(common, RESET,
ath_dbg(common, RESET,
ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
ath_dbg(common, RESET,
ath_dbg(common, RESET, "==== BB update: done ====\n\n");
ath_dbg(common, RESET,
ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
ath_dbg(ath9k_hw_common(ah), RESET,
ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
ath_dbg(common, RESET, "Setting CFG 0x%x\n",
ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
ath_dbg(common, RESET, "%s -> %s\n",
ath_dbg(ath9k_hw_common(ah), RESET,
ath_dbg(common, RESET, "serialize_regmode is %d\n",
ath_dbg(common, RESET,
ath_dbg(common, RESET, "PLL WAR, resetting the chip\n");
ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
ath_dbg(common, RESET,
ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
ath_dbg(common, RESET,
ath_dbg(common, RESET,
ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
ath_dbg(common, RESET,
hif_cnf_name(RESET) \
val = readl(priv->base + RESET);
writel(val, priv->base + RESET);
val = readl(priv->base + RESET);
val = readl(base + RESET);
writel(val, base + RESET);
val = readl(base + RESET);
writel(val, base + RESET);
return !!(readl(priv->base + RESET) & port_mask);
if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
(FIFO | TIMEOUT | RESET | SCAM_SEL));
(BUS_FREE | RESET))) {
else if (p_int & RESET) {
(PHASE | RESET))
while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET)) &&
while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
if (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
if (RDW_HARPOON((port + hp_intstat)) & RESET) {
(BUS_FREE | ICMD_COMP | ITAR_DISC | RESET))) {
if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
(RESET | TIMEOUT | SEL | BUS_FREE | AUTO_INT));
(RESET | PROG_HLT | TIMEOUT | AUTO_INT))) {
if (RDW_HARPOON((p_port + hp_intstat)) & RESET)
if (RDW_HARPOON((p_port + hp_intstat)) & (RESET | TIMEOUT)) {
(RESET | TIMEOUT | SEL | BUS_FREE | PHASE));
FPT_default_intena = RESET | RSEL | PROG_HLT | TIMEOUT |
if (read_iir & RESET) {
writew(RESET, dc->reg_fcr);
dc->last_ier = RESET;
if (interrupt & RESET)
if (INTEL_DSM_SUPPORTED(host, RESET)) {
if (INTEL_DSM_SUPPORTED(host, RESET)) {
outb(3, ES1688P(chip, RESET)); /* valid only for ESS chips, SB -> 1 */
outb(0, ES1688P(chip, RESET));
outb(1, SBP(chip, RESET));
outb(0, SBP(chip, RESET));
outb(3, SLSB_REG(chip, RESET));
inb(SLSB_REG(chip, RESET));
outb(0, SLSB_REG(chip, RESET));
outb(2, SLSB_REG(chip, RESET));
outb(0, SLSB_REG(chip, RESET));