drivers/gpu/drm/i915/display/g4x_dp.c

289

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);

drivers/gpu/drm/i915/display/g4x_dp.c

293

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);

drivers/gpu/drm/i915/display/g4x_dp.c

295

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);

drivers/gpu/drm/i915/display/g4x_dp.c

390

pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/i9xx_plane.c

1227

fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;

drivers/gpu/drm/i915/display/i9xx_plane.c

1228

fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;

drivers/gpu/drm/i915/display/i9xx_plane.c

747

*pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

2770

wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);

drivers/gpu/drm/i915/display/i9xx_wm.c

2771

wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);

drivers/gpu/drm/i915/display/i9xx_wm.c

2772

wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);

drivers/gpu/drm/i915/display/i9xx_wm.c

2773

wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);

drivers/gpu/drm/i915/display/i9xx_wm.c

2787

wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);

drivers/gpu/drm/i915/display/i9xx_wm.c

2788

wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);

drivers/gpu/drm/i915/display/i9xx_wm.c

3519

active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);

drivers/gpu/drm/i915/display/i9xx_wm.c

3520

active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);

drivers/gpu/drm/i915/display/i9xx_wm.c

3521

active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);

drivers/gpu/drm/i915/display/intel_audio.c

262

return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);

drivers/gpu/drm/i915/display/intel_bw.c

101

sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

102

sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

220

dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

222

sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

223

sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

225

sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);

drivers/gpu/drm/i915/display/intel_bw.c

226

sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);

drivers/gpu/drm/i915/display/intel_bw.c

82

dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

97

sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);

drivers/gpu/drm/i915/display/intel_bw.c

98

sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);

drivers/gpu/drm/i915/display/intel_casf.c

148

REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))

drivers/gpu/drm/i915/display/intel_casf.c

152

REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);

drivers/gpu/drm/i915/display/intel_casf.c

155

REG_FIELD_GET(FILTER_SIZE_MASK, sharp);

drivers/gpu/drm/i915/display/intel_cdclk.c

1811

size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;

drivers/gpu/drm/i915/display/intel_cdclk.c

1812

waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);

drivers/gpu/drm/i915/display/intel_color.c

1852

entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, ldw), 14);

drivers/gpu/drm/i915/display/intel_color.c

1853

entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, ldw), 14);

drivers/gpu/drm/i915/display/intel_color.c

1854

entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_RED_UDW_MASK, udw), 14);

drivers/gpu/drm/i915/display/intel_color.c

1886

entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_LDW_MASK, ldw), 10);

drivers/gpu/drm/i915/display/intel_color.c

1887

entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_LDW_MASK, ldw), 10);

drivers/gpu/drm/i915/display/intel_color.c

1888

entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UDW_MASK, udw), 10);

drivers/gpu/drm/i915/display/intel_color.c

840

entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8);

drivers/gpu/drm/i915/display/intel_color.c

841

entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8);

drivers/gpu/drm/i915/display/intel_color.c

842

entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8);

drivers/gpu/drm/i915/display/intel_color.c

889

u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) |

drivers/gpu/drm/i915/display/intel_color.c

890

REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8;

drivers/gpu/drm/i915/display/intel_color.c

891

u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) |

drivers/gpu/drm/i915/display/intel_color.c

892

REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8;

drivers/gpu/drm/i915/display/intel_color.c

893

u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) |

drivers/gpu/drm/i915/display/intel_color.c

894

REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8;

drivers/gpu/drm/i915/display/intel_color.c

904

int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

905

int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

906

int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

907

int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

908

int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

909

int b_mant = REG_FIELD_GET(PALETTE_10BIT_BLUE_MANT_MASK, udw);

drivers/gpu/drm/i915/display/intel_color.c

936

entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |

drivers/gpu/drm/i915/display/intel_color.c

937

REG_FIELD_GET(PALETTE_RED_MASK, ldw);

drivers/gpu/drm/i915/display/intel_color.c

938

entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |

drivers/gpu/drm/i915/display/intel_color.c

939

REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);

drivers/gpu/drm/i915/display/intel_color.c

940

entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |

drivers/gpu/drm/i915/display/intel_color.c

941

REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);

drivers/gpu/drm/i915/display/intel_color.c

959

entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10);

drivers/gpu/drm/i915/display/intel_color.c

960

entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10);

drivers/gpu/drm/i915/display/intel_color.c

961

entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);

drivers/gpu/drm/i915/display/intel_color.c

982

entry->red = REG_FIELD_GET(PREC_PALETTE_12P4_RED_UDW_MASK, udw) << 6 |

drivers/gpu/drm/i915/display/intel_color.c

983

REG_FIELD_GET(PREC_PALETTE_12P4_RED_LDW_MASK, ldw);

drivers/gpu/drm/i915/display/intel_color.c

984

entry->green = REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_UDW_MASK, udw) << 6 |

drivers/gpu/drm/i915/display/intel_color.c

985

REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_LDW_MASK, ldw);

drivers/gpu/drm/i915/display/intel_color.c

986

entry->blue = REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_UDW_MASK, udw) << 6 |

drivers/gpu/drm/i915/display/intel_color.c

987

REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_LDW_MASK, ldw);

drivers/gpu/drm/i915/display/intel_crt.c

100

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);

drivers/gpu/drm/i915/display/intel_crt.c

102

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);

drivers/gpu/drm/i915/display/intel_crt.c

717

vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;

drivers/gpu/drm/i915/display/intel_crt.c

718

vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;

drivers/gpu/drm/i915/display/intel_crt.c

720

vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;

drivers/gpu/drm/i915/display/intel_crt.c

721

vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;

drivers/gpu/drm/i915/display/intel_crt.c

757

u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;

drivers/gpu/drm/i915/display/intel_cursor.c

751

*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

195

if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

244

return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2723

unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2727

frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2731

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2732

tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2733

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2737

frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2741

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2742

tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2743

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2744

fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

207

REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

208

REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))

drivers/gpu/drm/i915/display/intel_ddi.c

2531

pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);

drivers/gpu/drm/i915/display/intel_ddi.c

3939

master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);

drivers/gpu/drm/i915/display/intel_ddi.c

3947

master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

4054

REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

4090

REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);

drivers/gpu/drm/i915/display/intel_display.c

2861

adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2862

adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2867

adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2868

adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2872

adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2873

adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2876

adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2877

adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2883

adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2884

adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2887

adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2888

adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

2946

REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,

drivers/gpu/drm/i915/display/intel_display.c

2947

REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);

drivers/gpu/drm/i915/display/intel_display.c

3091

pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);

drivers/gpu/drm/i915/display/intel_display.c

3093

pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

3351

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

drivers/gpu/drm/i915/display/intel_display.c

3442

pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);

drivers/gpu/drm/i915/display/intel_display.c

3444

pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

3446

pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);

drivers/gpu/drm/i915/display/intel_display.c

3981

pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;

drivers/gpu/drm/i915/display/intel_display.c

4018

pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);

drivers/gpu/drm/i915/display/intel_display.c

4021

REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);

drivers/gpu/drm/i915/display/intel_display_device.c

1542

gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);

drivers/gpu/drm/i915/display/intel_display_device.c

1543

gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);

drivers/gpu/drm/i915/display/intel_display_device.c

1544

gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);

drivers/gpu/drm/i915/display/intel_display_device.c

1901

if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) ==

drivers/gpu/drm/i915/display/intel_display_device.c

1905

if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) ==

drivers/gpu/drm/i915/display/intel_display_power_well.c

1610

actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |

drivers/gpu/drm/i915/display/intel_display_power_well.c

1613

actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |

drivers/gpu/drm/i915/display/intel_display_regs.h

2372

#define DDI_PORT_WIDTH_GET(regval) DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \

drivers/gpu/drm/i915/display/intel_dmc.c

563

REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;

drivers/gpu/drm/i915/display/intel_dp_aux.c

418

recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

814

stream_type = REG_FIELD_GET(AUTH_STREAM_TYPE_MASK, val);

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

836

stream_type = REG_FIELD_GET(STREAM_TYPE_STATUS_MASK, val);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

387

return REG_FIELD_GET(GRC_CODE_MASK, val);

drivers/gpu/drm/i915/display/intel_dpll.c

535

clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

536

clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

537

clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

538

clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

539

clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);

drivers/gpu/drm/i915/display/intel_dpll.c

567

clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

drivers/gpu/drm/i915/display/intel_dpll.c

568

clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;

drivers/gpu/drm/i915/display/intel_dpll.c

570

clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);

drivers/gpu/drm/i915/display/intel_dpll.c

571

clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);

drivers/gpu/drm/i915/display/intel_dpll.c

572

clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);

drivers/gpu/drm/i915/display/intel_dpll.c

573

clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2393

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2395

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2397

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2398

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2399

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);

drivers/gpu/drm/i915/display/intel_dram.c

276

return REG_FIELD_GET(SKL_DIMM_S_SIZE_MASK, val) * 8;

drivers/gpu/drm/i915/display/intel_dram.c

281

return REG_FIELD_GET(SKL_DIMM_L_SIZE_MASK, val) * 8;

drivers/gpu/drm/i915/display/intel_dram.c

293

return 8 << REG_FIELD_GET(SKL_DIMM_S_WIDTH_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

309

return 8 << REG_FIELD_GET(SKL_DIMM_L_WIDTH_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

321

return REG_FIELD_GET(SKL_DIMM_S_RANK_MASK, val) + 1;

drivers/gpu/drm/i915/display/intel_dram.c

329

return REG_FIELD_GET(SKL_DIMM_L_RANK_MASK, val) + 1;

drivers/gpu/drm/i915/display/intel_dram.c

335

return REG_FIELD_GET(ICL_DIMM_S_SIZE_MASK, val) * 8 / 2;

drivers/gpu/drm/i915/display/intel_dram.c

340

return REG_FIELD_GET(ICL_DIMM_L_SIZE_MASK, val) * 8 / 2;

drivers/gpu/drm/i915/display/intel_dram.c

352

return 8 << REG_FIELD_GET(ICL_DIMM_S_WIDTH_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

368

return 8 << REG_FIELD_GET(ICL_DIMM_L_WIDTH_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

380

return REG_FIELD_GET(ICL_DIMM_S_RANK_MASK, val) + 1;

drivers/gpu/drm/i915/display/intel_dram.c

388

return REG_FIELD_GET(ICL_DIMM_L_RANK_MASK, val) + 1;

drivers/gpu/drm/i915/display/intel_dram.c

772

switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {

drivers/gpu/drm/i915/display/intel_dram.c

804

dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

805

dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);

drivers/gpu/drm/i915/display/intel_dram.c

809

dram_info->ecc_impacting_de_bw = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);

drivers/gpu/drm/i915/display/intel_dvo.c

156

*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

100

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

102

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

104

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

121

REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

122

REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

98

log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),

drivers/gpu/drm/i915/display/intel_flipq.c

247

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),

drivers/gpu/drm/i915/display/intel_flipq.c

248

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),

drivers/gpu/drm/i915/display/intel_flipq.c

249

REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),

drivers/gpu/drm/i915/display/intel_flipq.c

250

REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),

drivers/gpu/drm/i915/display/intel_flipq.c

251

REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp));

drivers/gpu/drm/i915/display/intel_hti.c

42

return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);

drivers/gpu/drm/i915/display/intel_lvds.c

166

pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

167

pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

168

pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

171

pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

172

pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

175

pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

176

val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);

drivers/gpu/drm/i915/display/intel_lvds.c

96

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);

drivers/gpu/drm/i915/display/intel_lvds.c

98

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);

drivers/gpu/drm/i915/display/intel_overlay.c

955

ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);

drivers/gpu/drm/i915/display/intel_overlay.c

964

ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);

drivers/gpu/drm/i915/display/intel_pfit.c

631

pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);

drivers/gpu/drm/i915/display/intel_pfit.c

641

REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),

drivers/gpu/drm/i915/display/intel_pfit.c

642

REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),

drivers/gpu/drm/i915/display/intel_pfit.c

643

REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),

drivers/gpu/drm/i915/display/intel_pfit.c

644

REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));

drivers/gpu/drm/i915/display/intel_pfit.c

721

pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);

drivers/gpu/drm/i915/display/intel_pmdemand.c

423

REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

425

REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

427

REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

429

REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

432

REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);

drivers/gpu/drm/i915/display/intel_pmdemand.c

434

REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);

drivers/gpu/drm/i915/display/intel_pmdemand.c

438

REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

441

REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

443

REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);

drivers/gpu/drm/i915/display/intel_pmdemand.c

446

REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);

drivers/gpu/drm/i915/display/intel_pmdemand.c

541

u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \

drivers/gpu/drm/i915/display/intel_pps.c

1387

seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

1388

seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

1389

seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);

drivers/gpu/drm/i915/display/intel_pps.c

1390

seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);

drivers/gpu/drm/i915/display/intel_pps.c

1397

power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div);

drivers/gpu/drm/i915/display/intel_pps.c

1399

power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl);

drivers/gpu/drm/i915/display/intel_psr.c

1947

pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);

drivers/gpu/drm/i915/display/intel_psr.c

4155

status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);

drivers/gpu/drm/i915/display/intel_psr.c

4171

status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val);

drivers/gpu/drm/i915/display/intel_psr.c

4290

REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1930

refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1932

frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1935

frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1936

frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1937

frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1940

multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1942

tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);

drivers/gpu/drm/i915/display/intel_vdsc.c

1003

vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

1009

vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

1014

vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

1015

vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

926

vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

927

vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

938

vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

948

vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;

drivers/gpu/drm/i915/display/intel_vdsc.c

949

vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

954

vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

955

vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

960

vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

961

vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

966

vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

967

vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

972

vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

973

vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

974

vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

975

vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

980

vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

981

vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

986

vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

987

vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

992

vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

997

vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vdsc.c

998

vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);

drivers/gpu/drm/i915/display/intel_vga.c

58

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);

drivers/gpu/drm/i915/display/intel_vga.c

60

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);

drivers/gpu/drm/i915/display/intel_vrr.c

1034

REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);

drivers/gpu/drm/i915/display/intel_vrr.c

1038

REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);

drivers/gpu/drm/i915/display/intel_vrr.c

1078

REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);

drivers/gpu/drm/i915/display/intel_vrr.c

1080

REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);

drivers/gpu/drm/i915/display/intel_vrr.c

1151

if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)

drivers/gpu/drm/i915/display/intel_vrr.c

1165

if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)

drivers/gpu/drm/i915/display/skl_scaler.c

1000

REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));

drivers/gpu/drm/i915/display/skl_scaler.c

997

REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),

drivers/gpu/drm/i915/display/skl_scaler.c

998

REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),

drivers/gpu/drm/i915/display/skl_scaler.c

999

REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),

drivers/gpu/drm/i915/display/skl_universal_plane.c

3093

alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3095

alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3191

fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3192

fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3197

fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;

drivers/gpu/drm/i915/display/skl_watermark.c

113

return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);

drivers/gpu/drm/i915/display/skl_watermark.c

2890

latency = REG_FIELD_GET(LNL_PKG_C_LATENCY_MASK,

drivers/gpu/drm/i915/display/skl_watermark.c

2971

level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

2972

level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3266

wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3267

wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3270

wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3271

wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3274

wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3275

wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3292

wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3293

wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3294

wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3295

wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3305

wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3306

wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3307

wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

3308

wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

673

REG_FIELD_GET(PLANE_BUF_START_MASK, reg),

drivers/gpu/drm/i915/display/skl_watermark.c

674

REG_FIELD_GET(PLANE_BUF_END_MASK, reg));

drivers/gpu/drm/i915/display/skl_watermark.c

702

*min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val);

drivers/gpu/drm/i915/display/skl_watermark.c

703

*interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

903

gms = REG_FIELD_GET(GMS_MASK, ggc);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

772

vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

773

vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

777

gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);

drivers/gpu/drm/i915/gt/intel_gt.c

320

REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

drivers/gpu/drm/i915/gt/intel_gt.c

321

REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

drivers/gpu/drm/i915/gt/intel_gt.c

342

REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),

drivers/gpu/drm/i915/gt/intel_gt.c

343

REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

drivers/gpu/drm/i915/gt/intel_gt.c

344

REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

102

freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

81

freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

125

gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK,

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

138

fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

142

fuse = REG_FIELD_GET(GT_L3_EXC_MASK,

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

291

switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

359

REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));

drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c

625

mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?

drivers/gpu/drm/i915/gt/intel_rps.c

1130

caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap);

drivers/gpu/drm/i915/gt/intel_rps.c

1131

caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap);

drivers/gpu/drm/i915/gt/intel_rps.c

1132

caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe);

drivers/gpu/drm/i915/gt/intel_rps.c

1151

caps->rp1_freq = REG_FIELD_GET(RPE_MASK,

drivers/gpu/drm/i915/gt/intel_rps.c

2095

cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2097

cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2099

cagf = REG_FIELD_GET(RPE_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2101

cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2103

cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2105

cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);

drivers/gpu/drm/i915/gt/intel_rps.c

2107

cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));

drivers/gpu/drm/i915/gt/intel_sseu.c

241

eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK,

drivers/gpu/drm/i915/gt/intel_sseu.c

275

s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,

drivers/gpu/drm/i915/gt/intel_sseu.c

282

eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,

drivers/gpu/drm/i915/gt/intel_sseu.c

312

s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,

drivers/gpu/drm/i915/gt/intel_sseu.c

318

eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,

drivers/gpu/drm/i915/gt/intel_sseu.c

341

REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) |

drivers/gpu/drm/i915/gt/intel_sseu.c

342

REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);

drivers/gpu/drm/i915/gt/intel_sseu.c

350

REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) |

drivers/gpu/drm/i915/gt/intel_sseu.c

351

REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);

drivers/gpu/drm/i915/gt/intel_sseu.c

387

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

398

subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

491

sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

499

subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2);

drivers/gpu/drm/i915/gt/intel_sseu.c

504

REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0);

drivers/gpu/drm/i915/gt/intel_sseu.c

506

REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) |

drivers/gpu/drm/i915/gt/intel_sseu.c

507

REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK);

drivers/gpu/drm/i915/gt/intel_sseu.c

509

REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) |

drivers/gpu/drm/i915/gt/intel_sseu.c

510

REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK);

drivers/gpu/drm/i915/gt/intel_sseu.c

598

switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) {

drivers/gpu/drm/i915/gt/intel_sseu.c

600

MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1));

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c

21

return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c

42

return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE,

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

110

u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

111

u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

207

REG_FIELD_GET(GS_BOOTROM_MASK, status),

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

208

REG_FIELD_GET(GS_UKERNEL_MASK, status));

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

214

u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

215

u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

220

REG_FIELD_GET(GS_MIA_IN_RESET, status),

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

222

REG_FIELD_GET(GS_MIA_MASK, status),

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

223

REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

377

return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

388

return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

1293

return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);

drivers/gpu/drm/i915/gvt/edid.c

499

msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);

drivers/gpu/drm/i915/gvt/handlers.c

1427

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

1454

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

591

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,

drivers/gpu/drm/i915/gvt/handlers.c

594

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

drivers/gpu/drm/i915/gvt/handlers.c

596

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,

drivers/gpu/drm/i915/gvt/handlers.c

598

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,

drivers/gpu/drm/i915/gvt/handlers.c

600

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,

drivers/gpu/drm/i915/i915_hwmon.c

110

reg_value = REG_FIELD_GET(field_msk, reg_value);

drivers/gpu/drm/i915/i915_hwmon.c

180

x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);

drivers/gpu/drm/i915/i915_hwmon.c

181

y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);

drivers/gpu/drm/i915/i915_hwmon.c

224

x = REG_FIELD_GET(PKG_MAX_WIN_X, r);

drivers/gpu/drm/i915/i915_hwmon.c

225

y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);

drivers/gpu/drm/i915/i915_hwmon.c

340

*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;

drivers/gpu/drm/i915/i915_hwmon.c

372

*val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);

drivers/gpu/drm/i915/i915_hwmon.c

430

min = REG_FIELD_GET(PKG_MIN_PWR, r);

drivers/gpu/drm/i915/i915_hwmon.c

432

max = REG_FIELD_GET(PKG_MAX_PWR, r);

drivers/gpu/drm/i915/i915_hwmon.c

520

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/gpu/drm/i915/i915_hwmon.c

637

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/gpu/drm/i915/i915_hwmon.c

888

hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);

drivers/gpu/drm/i915/i915_hwmon.c

889

hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);

drivers/gpu/drm/i915/i915_hwmon.c

890

hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);

drivers/gpu/drm/i915/i915_perf.c

3205

shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,

drivers/gpu/drm/i915/intel_clock_gating.c

246

if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)

drivers/gpu/drm/i915/intel_device_info.c

312

ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);

drivers/gpu/drm/i915/intel_device_info.c

313

ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);

drivers/gpu/drm/i915/intel_device_info.c

314

ip->step = REG_FIELD_GET(GMD_ID_STEP, val);

drivers/gpu/drm/xe/regs/xe_irq_regs.h

56

#define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)

drivers/gpu/drm/xe/regs/xe_irq_regs.h

57

#define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)

drivers/gpu/drm/xe/regs/xe_irq_regs.h

58

#define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)

drivers/gpu/drm/xe/xe_device.c

1214

REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid),

drivers/gpu/drm/xe/xe_device.c

1215

REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid),

drivers/gpu/drm/xe/xe_device.c

1216

REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid));

drivers/gpu/drm/xe/xe_device_sysfs.c

104

major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low);

drivers/gpu/drm/xe/xe_device_sysfs.c

105

minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low);

drivers/gpu/drm/xe/xe_device_sysfs.c

106

hotfix = REG_FIELD_GET(HOTFIX_VERSION_MASK, ver_high);

drivers/gpu/drm/xe/xe_device_sysfs.c

107

build = REG_FIELD_GET(BUILD_VERSION_MASK, ver_high);

drivers/gpu/drm/xe/xe_device_sysfs.c

130

if (REG_FIELD_GET(VR_PARAMS_PROVISIONED, cap)) {

drivers/gpu/drm/xe/xe_device_sysfs.c

141

major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low);

drivers/gpu/drm/xe/xe_device_sysfs.c

142

minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low);

drivers/gpu/drm/xe/xe_device_sysfs.c

143

hotfix = REG_FIELD_GET(HOTFIX_VERSION_MASK, ver_high);

drivers/gpu/drm/xe/xe_device_sysfs.c

144

build = REG_FIELD_GET(BUILD_VERSION_MASK, ver_high);

drivers/gpu/drm/xe/xe_device_sysfs.c

172

REG_FIELD_GET(V1_FAN_SUPPORTED, cap))

drivers/gpu/drm/xe/xe_device_sysfs.c

175

REG_FIELD_GET(VR_PARAMS_SUPPORTED, cap))

drivers/gpu/drm/xe/xe_device_sysfs.c

234

cap = REG_FIELD_GET(LINK_DOWNGRADE, val);

drivers/gpu/drm/xe/xe_device_sysfs.c

253

return ret ?: sysfs_emit(buf, "%u\n", REG_FIELD_GET(DGFX_LINK_DOWNGRADE_STATUS, val));

drivers/gpu/drm/xe/xe_device_sysfs.c

93

if (REG_FIELD_GET(V1_FAN_PROVISIONED, cap)) {

drivers/gpu/drm/xe/xe_eu_stall.c

419

write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);

drivers/gpu/drm/xe/xe_eu_stall.c

684

write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);

drivers/gpu/drm/xe/xe_gsc_proxy.c

71

return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fwsts1) ==

drivers/gpu/drm/xe/xe_gt_clock.c

26

u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,

drivers/gpu/drm/xe/xe_gt_clock.c

67

freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);

drivers/gpu/drm/xe/xe_gt_mcr.c

301

u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,

drivers/gpu/drm/xe/xe_gt_mcr.c

303

u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,

drivers/gpu/drm/xe/xe_gt_mcr.c

314

u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,

drivers/gpu/drm/xe/xe_gt_mcr.c

326

u32 fuse = REG_FIELD_GET(L3BANK_MASK,

drivers/gpu/drm/xe/xe_gt_mcr.c

336

u32 mask = REG_FIELD_GET(MEML3_EN_MASK,

drivers/gpu/drm/xe/xe_gt_mcr.c

460

u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK,

drivers/gpu/drm/xe/xe_gt_topology.c

157

u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

159

u32 bank_val = REG_FIELD_GET(XE3_L3BANK_ENABLE, mirror_l3bank_enable);

drivers/gpu/drm/xe/xe_gt_topology.c

166

u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

167

u32 bank_val = REG_FIELD_GET(XE2_GT_L3_MODE_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

175

u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

177

u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4);

drivers/gpu/drm/xe/xe_gt_topology.c

186

u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

187

u32 bank_val = REG_FIELD_GET(XEHPC_GT_L3_MODE_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

196

u32 mask = REG_FIELD_GET(MEML3_EN_MASK, fuse3);

drivers/gpu/drm/xe/xe_gt_topology.c

202

u32 mask = REG_FIELD_GET(XELP_GT_L3_MODE_MASK, ~fuse3);

drivers/gpu/drm/xe/xe_guc.c

1016

u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status);

drivers/gpu/drm/xe/xe_guc.c

1017

u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);

drivers/gpu/drm/xe/xe_guc.c

1020

REG_FIELD_GET(GS_MIA_IN_RESET, status),

drivers/gpu/drm/xe/xe_guc.c

1022

REG_FIELD_GET(GS_MIA_MASK, status),

drivers/gpu/drm/xe/xe_guc.c

1023

REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));

drivers/gpu/drm/xe/xe_guc.c

1073

ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status);

drivers/gpu/drm/xe/xe_guc.c

1074

bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status);

drivers/gpu/drm/xe/xe_guc.c

1703

REG_FIELD_GET(GS_BOOTROM_MASK, status));

drivers/gpu/drm/xe/xe_guc.c

1705

REG_FIELD_GET(GS_UKERNEL_MASK, status));

drivers/gpu/drm/xe/xe_guc.c

1707

REG_FIELD_GET(GS_MIA_MASK, status));

drivers/gpu/drm/xe/xe_guc.c

1766

u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val);

drivers/gpu/drm/xe/xe_guc_ads.c

856

REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);

drivers/gpu/drm/xe/xe_guc_engine_activity.c

321

return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);

drivers/gpu/drm/xe/xe_guc_pc.c

376

return decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));

drivers/gpu/drm/xe/xe_guc_pc.c

389

return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));

drivers/gpu/drm/xe/xe_guc_pc.c

404

return REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_guc_pc.c

413

return REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_guc_pc.c

425

return REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_guc_pc.c

438

return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_guc_pc.c

456

freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);

drivers/gpu/drm/xe/xe_guc_pc.c

459

freq = REG_FIELD_GET(CAGF_MASK, freq);

drivers/gpu/drm/xe/xe_guc_pc.c

472

freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);

drivers/gpu/drm/xe/xe_guc_pc.c

732

gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);

drivers/gpu/drm/xe/xe_guc_pc.c

735

gt_c_state = REG_FIELD_GET(RCN_MASK, reg);

drivers/gpu/drm/xe/xe_guc_pc.c

788

pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg));

drivers/gpu/drm/xe/xe_guc_pc.c

790

pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg));

drivers/gpu/drm/xe/xe_guc_pc.c

805

pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_guc_pc.c

806

pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

drivers/gpu/drm/xe/xe_hw_engine.c

592

idledly = REG_FIELD_GET(IDLE_DELAY, idledly);

drivers/gpu/drm/xe/xe_hw_engine.c

594

maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);

drivers/gpu/drm/xe/xe_hw_engine.c

696

vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse);

drivers/gpu/drm/xe/xe_hw_engine.c

697

vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse);

drivers/gpu/drm/xe/xe_hw_engine.c

722

u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,

drivers/gpu/drm/xe/xe_hw_engine.c

738

return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,

drivers/gpu/drm/xe/xe_hw_engine.c

800

ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);

drivers/gpu/drm/xe/xe_hwmon.c

1008

*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;

drivers/gpu/drm/xe/xe_hwmon.c

1020

*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *

drivers/gpu/drm/xe/xe_hwmon.c

1021

(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *

drivers/gpu/drm/xe/xe_hwmon.c

1509

hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);

drivers/gpu/drm/xe/xe_hwmon.c

1510

hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);

drivers/gpu/drm/xe/xe_hwmon.c

1511

hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);

drivers/gpu/drm/xe/xe_hwmon.c

354

reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

362

min = REG_FIELD_GET(PKG_MIN_PWR, pkg_pwr);

drivers/gpu/drm/xe/xe_hwmon.c

363

max = REG_FIELD_GET(PKG_MAX_PWR, pkg_pwr);

drivers/gpu/drm/xe/xe_hwmon.c

468

reg_val = REG_FIELD_GET(PKG_TDP, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

566

x = REG_FIELD_GET(PWR_LIM_TIME_X, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

567

y = REG_FIELD_GET(PWR_LIM_TIME_Y, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

620

x = REG_FIELD_GET(PKG_MAX_WIN_X, r);

drivers/gpu/drm/xe/xe_hwmon.c

621

y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);

drivers/gpu/drm/xe/xe_hwmon.c

775

hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config);

drivers/gpu/drm/xe/xe_hwmon.c

816

data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);

drivers/gpu/drm/xe/xe_hwmon.c

818

data = REG_FIELD_GET(TEMP_MASK, data);

drivers/gpu/drm/xe/xe_hwmon.c

872

*value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/gpu/drm/xe/xe_hwmon.c

915

*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);

drivers/gpu/drm/xe/xe_lrc.c

1853

return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2;

drivers/gpu/drm/xe/xe_lrc.c

1856

return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2;

drivers/gpu/drm/xe/xe_lrc.c

1866

u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header);

drivers/gpu/drm/xe/xe_lrc.c

1935

u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw);

drivers/gpu/drm/xe/xe_lrc.c

1936

u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw);

drivers/gpu/drm/xe/xe_lrc.c

1937

u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw);

drivers/gpu/drm/xe/xe_lrc.c

2087

u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw);

drivers/gpu/drm/xe/xe_lrc.c

2135

*dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw),

drivers/gpu/drm/xe/xe_lrc.c

2388

u16 class = REG_FIELD_GET(ENGINE_CLASS_ID, engine_id);

drivers/gpu/drm/xe/xe_lrc.c

2389

u16 instance = REG_FIELD_GET(ENGINE_INSTANCE_ID, engine_id);

drivers/gpu/drm/xe/xe_mocs.c

284

REG_FIELD_GET(L3_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

285

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

291

REG_FIELD_GET(L3_UPPER_IDX_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

292

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

315

REG_FIELD_GET(LE_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

316

REG_FIELD_GET(LE_TGT_CACHE_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

317

REG_FIELD_GET(LE_LRUM_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

320

REG_FIELD_GET(LE_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

321

REG_FIELD_GET(LE_PFM_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

323

REG_FIELD_GET(LE_COS_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

324

REG_FIELD_GET(LE_SSE_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

390

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

397

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

433

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

438

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

516

REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

559

REG_FIELD_GET(XE2_L3_CLOS_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

560

REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),

drivers/gpu/drm/xe/xe_oa.c

1924

shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);

drivers/gpu/drm/xe/xe_oa.c

458

REG_FIELD_GET(OAG_OACONTROL_OA_CCS_SELECT_MASK, val) == stream->hwe->instance);

drivers/gpu/drm/xe/xe_pat.c

271

return REG_FIELD_GET(XE2_L3_POLICY, xe->pat.table[pat_index].value);

drivers/gpu/drm/xe/xe_pat.c

423

REG_FIELD_GET(XE2_L3_CLOS, pat),

drivers/gpu/drm/xe/xe_pat.c

424

REG_FIELD_GET(XE2_L3_POLICY, pat),

drivers/gpu/drm/xe/xe_pat.c

425

REG_FIELD_GET(XE2_L4_POLICY, pat),

drivers/gpu/drm/xe/xe_pat.c

426

REG_FIELD_GET(XE2_COH_MODE, pat),

drivers/gpu/drm/xe/xe_pat.c

434

REG_FIELD_GET(XE2_L3_CLOS, pat),

drivers/gpu/drm/xe/xe_pat.c

435

REG_FIELD_GET(XE2_L3_POLICY, pat),

drivers/gpu/drm/xe/xe_pat.c

436

REG_FIELD_GET(XE2_L4_POLICY, pat),

drivers/gpu/drm/xe/xe_pat.c

437

REG_FIELD_GET(XE2_COH_MODE, pat),

drivers/gpu/drm/xe/xe_pat.c

65

u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);

drivers/gpu/drm/xe/xe_pat.c

74

REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat),

drivers/gpu/drm/xe/xe_pat.c

75

REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat);

drivers/gpu/drm/xe/xe_pat.c

81

REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat),

drivers/gpu/drm/xe/xe_pat.c

82

REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat);

drivers/gpu/drm/xe/xe_pci.c

598

*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);

drivers/gpu/drm/xe/xe_pci.c

599

*revid = REG_FIELD_GET(GMD_ID_REVID, val);

drivers/gpu/drm/xe/xe_pci.c

759

tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;

drivers/gpu/drm/xe/xe_query.c

416

REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid);

drivers/gpu/drm/xe/xe_query.c

418

REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid);

drivers/gpu/drm/xe/xe_query.c

420

REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid);

drivers/gpu/drm/xe/xe_survivability_mode.c

146

survivability->version = REG_FIELD_GET(BREADCRUMB_VERSION, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

149

survivability->fdo_mode = REG_FIELD_GET(FDO_MODE, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

160

for (id = REG_FIELD_GET(AUXINFO_REG_OFFSET, reg_value);

drivers/gpu/drm/xe/xe_survivability_mode.c

162

id = REG_FIELD_GET(AUXINFO_HISTORY_OFFSET, info[id]))

drivers/gpu/drm/xe/xe_survivability_mode.c

386

survivability->boot_status = REG_FIELD_GET(BOOT_STATUS, data);

drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c

151

gms = REG_FIELD_GET(GMS_MASK, ggc);

drivers/gpu/drm/xe/xe_vram.c

156

*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;

drivers/gpu/drm/xe/xe_vram.c

157

*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;

drivers/gpu/drm/xe/xe_vram.c

79

nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);

drivers/gpu/drm/xe/xe_vram.c

83

offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);

drivers/gpu/drm/xe/xe_vram.c

86

offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);

drivers/gpu/drm/xe/xe_vram.c

99

offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;