REG_CTRL
val = readl_relaxed(chan->base + REG_CTRL);
writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL);
val = readl_relaxed(chan->base + REG_CTRL);
writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL);
return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0;
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
ctrl = readl(i2c->regs + REG_CTRL);
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl,
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
config = tiadc_readl(adc_dev, REG_CTRL);
tiadc_writel(adc_dev, REG_CTRL, config);
tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB));
idle = tiadc_readl(adc_dev, REG_CTRL);
tiadc_writel(adc_dev, REG_CTRL, idle | CNTRLREG_POWERDOWN);
restore = tiadc_readl(adc_dev, REG_CTRL);
tiadc_writel(adc_dev, REG_CTRL, restore);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB);
regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
regmap_write(tscadc->regmap, REG_CTRL, ctrl);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB);
regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_REF_CLK_SEL_MASK,
regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_FSEL_MASK,
regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET);
regmap_clear_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET);
regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT);
regmap_set_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET);
val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
ssd202d_rtc_read_reg(priv, REG_CTRL, SW0_RD_BIT, &sw0);
ssd202d_rtc_read_reg(priv, REG_CTRL, BASE_RD_BIT, &base);
val = readw(priv->base + REG_CTRL);
writew(val | CNT_RST_BIT, priv->base + REG_CTRL);
writew(val & ~CNT_RST_BIT, priv->base + REG_CTRL);
ssd202d_rtc_write_reg(priv, REG_CTRL, BASE_WR_BIT, seconds);
ssd202d_rtc_write_reg(priv, REG_CTRL, SW0_WR_BIT, 1);
regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
rval |= lm3630a_update(pchip, REG_CTRL, 0x14, pdata->leda_ctrl);
rval |= lm3630a_update(pchip, REG_CTRL, 0x0B, pdata->ledb_ctrl);
rval = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00);
ret = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00);
ret |= lm3630a_update(pchip, REG_CTRL, LM3630A_LEDA_ENABLE, 0);
ret |= lm3630a_update(pchip, REG_CTRL,
rval = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00);
ret = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00);
ret |= lm3630a_update(pchip, REG_CTRL, LM3630A_LEDB_ENABLE, 0);
ret |= lm3630a_update(pchip, REG_CTRL,
rval = lm3630a_update(pchip, REG_CTRL, 0x80, 0x00);
xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
xilinx_fb_out32(drvdata, REG_CTRL, 0);
xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
xilinx_fb_out32(drvdata, REG_CTRL, 0);
xilinx_fb_out32(drvdata, REG_CTRL, 0);