Symbol: REG_ANA_GLB_D0
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
219
mtk_phy_update_bits(xfi_tphy->base + REG_ANA_GLB_D0,
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
225
mtk_phy_set_bits(xfi_tphy->base + REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);