arch/m68k/kernel/traps.c

988

if (ssw & RB)

arch/powerpc/xmon/ppc-opc.c

3096

{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},

arch/powerpc/xmon/ppc-opc.c

3098

{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},

arch/powerpc/xmon/ppc-opc.c

3100

{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3101

{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3107

{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3109

{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3141

{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},

arch/powerpc/xmon/ppc-opc.c

3143

{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},

arch/powerpc/xmon/ppc-opc.c

3146

{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},

arch/powerpc/xmon/ppc-opc.c

3171

{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},

arch/powerpc/xmon/ppc-opc.c

3173

{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},

arch/powerpc/xmon/ppc-opc.c

3176

{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3178

{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3179

{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3180

{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3181

{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3182

{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3196

{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3197

{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3206

{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3207

{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3208

{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3209

{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3219

{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3221

{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3222

{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3223

{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3232

{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3233

{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3234

{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3235

{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3236

{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3237

{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3247

{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3248

{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3255

{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3256

{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3257

{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3258

{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3259

{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3262

{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3264

{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3265

{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

3267

{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},

arch/powerpc/xmon/ppc-opc.c

3268

{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3282

{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3285

{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3286

{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3287

{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3289

{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3290

{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3293

{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3294

{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3295

{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3296

{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3297

{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3300

{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3302

{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3306

{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3307

{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3308

{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3309

{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3310

{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3311

{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3312

{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3313

{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3314

{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3327

{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},

arch/powerpc/xmon/ppc-opc.c

3329

{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3331

{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3339

{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3340

{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3342

{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3345

{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3346

{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3348

{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3349

{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3350

{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3351

{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3352

{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3353

{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3354

{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3355

{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3356

{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3358

{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3359

{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3360

{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3361

{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3363

{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3364

{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3372

{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3373

{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3375

{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3377

{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3378

{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3380

{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3381

{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3382

{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3383

{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3384

{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3385

{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3386

{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3387

{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3388

{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3389

{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3391

{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3392

{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3393

{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3394

{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3395

{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3396

{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3397

{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3398

{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3402

{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3403

{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3404

{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3405

{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3406

{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3407

{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3408

{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3409

{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3410

{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3411

{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3412

{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3413

{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3414

{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3415

{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3416

{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3417

{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3418

{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3420

{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3421

{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3422

{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3423

{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3424

{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3427

{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3430

{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3434

{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3439

{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3443

{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3446

{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3447

{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3448

{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3450

{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3452

{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3454

{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3455

{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3456

{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3458

{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3460

{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3462

{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3464

{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3466

{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3468

{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3470

{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3472

{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3485

{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3486

{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3487

{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3488

{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3489

{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3490

{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3500

{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3501

{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3510

{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3511

{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3512

{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3513

{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3518

{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3524

{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3526

{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3527

{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3529

{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3530

{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3532

{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3533

{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3534

{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3535

{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3538

{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3539

{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3540

{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3541

{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3542

{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3543

{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3544

{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3545

{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3555

{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3557

{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3559

{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3561

{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3563

{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3564

{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3565

{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3566

{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3567

{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3568

{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3569

{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3570

{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3571

{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3574

{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3575

{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3576

{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3577

{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3578

{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3579

{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3580

{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3581

{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3582

{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3594

{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3595

{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3606

{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3611

{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3618

{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3619

{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3620

{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3621

{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3625

{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3627

{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3629

{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3630

{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3633

{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3637

{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3638

{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3641

{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3642

{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3644

{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3645

{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3646

{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3647

{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3648

{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3649

{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3650

{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3651

{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3652

{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3653

{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3654

{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3656

{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3658

{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3665

{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3667

{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3670

{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3671

{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3672

{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3673

{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3674

{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3675

{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3676

{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3677

{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3678

{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3680

{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3689

{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3691

{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3692

{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3696

{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3697

{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3698

{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3699

{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3700

{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3701

{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3702

{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3703

{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3704

{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3705

{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3706

{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3707

{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3708

{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3709

{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3710

{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3711

{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3713

{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3719

{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3720

{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3723

{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3724

{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3725

{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3726

{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3727

{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3728

{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3729

{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3730

{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3787

{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3788

{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3797

{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3798

{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3799

{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3800

{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3810

{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3811

{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3818

{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3819

{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3820

{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3821

{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3822

{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4601

{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4602

{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4604

{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4605

{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4606

{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4607

{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4608

{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4609

{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4647

{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4648

{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},

arch/powerpc/xmon/ppc-opc.c

4649

{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4650

{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},

arch/powerpc/xmon/ppc-opc.c

4652

{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},

arch/powerpc/xmon/ppc-opc.c

4653

{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},

arch/powerpc/xmon/ppc-opc.c

4655

{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4656

{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4657

{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4658

{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4660

{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4661

{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4662

{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4663

{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4664

{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4665

{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4666

{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4667

{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4668

{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4669

{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4670

{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4671

{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4672

{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4673

{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4674

{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4675

{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4676

{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4677

{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4678

{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4679

{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4680

{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4681

{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4682

{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4683

{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4684

{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4685

{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4686

{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4687

{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4689

{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4690

{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4691

{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4692

{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4694

{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4695

{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4696

{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4698

{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4699

{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4700

{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

4701

{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4702

{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4703

{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

4705

{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4706

{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4708

{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4709

{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4710

{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4711

{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4713

{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4714

{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4716

{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4718

{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4722

{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4723

{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4728

{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4730

{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4732

{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4734

{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4735

{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4737

{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4738

{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4739

{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4740

{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4747

{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4748

{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4750

{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4751

{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4753

{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4754

{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4756

{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4761

{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4763

{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4764

{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4765

{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4766

{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4768

{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4769

{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4770

{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4772

{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4774

{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4776

{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4778

{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4780

{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4782

{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4784

{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},

arch/powerpc/xmon/ppc-opc.c

4786

{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4787

{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

4788

{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4789

{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

4794

{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4796

{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4798

{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

4800

{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4802

{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

4803

{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4808

{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4809

{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4815

{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4817

{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4818

{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4819

{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4820

{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4821

{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4822

{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4823

{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4824

{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4825

{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4826

{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4827

{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4828

{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4829

{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4830

{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4831

{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4832

{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4834

{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4835

{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4836

{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4838

{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4839

{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4841

{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4842

{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4848

{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4850

{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4851

{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},

arch/powerpc/xmon/ppc-opc.c

4853

{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4855

{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4859

{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4860

{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4865

{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4866

{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4868

{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4870

{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4876

{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4878

{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4880

{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

4885

{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4887

{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4889

{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4895

{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4897

{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4898

{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4900

{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4901

{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4902

{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4903

{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4905

{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4906

{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4907

{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4908

{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4910

{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4912

{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

4913

{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4923

{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4924

{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4926

{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4928

{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4930

{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4931

{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4933

{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4934

{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4936

{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4937

{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4941

{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4943

{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4947

{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4949

{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4950

{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4952

{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},

arch/powerpc/xmon/ppc-opc.c

4954

{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

4955

{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4964

{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

4966

{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4969

{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

4970

{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4977

{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4979

{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4981

{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4982

{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4994

{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

5003

{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5005

{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5007

{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5009

{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5010

{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5012

{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5013

{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5015

{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5017

{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5019

{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5021

{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5022

{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5029

{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5030

{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5037

{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5038

{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5039

{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5040

{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5042

{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5043

{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

5044

{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5045

{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5051

{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5052

{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5053

{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5054

{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5056

{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5061

{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5063

{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5068

{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5070

{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5072

{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5074

{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5075

{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5076

{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5078

{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5080

{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5081

{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5082

{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5083

{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5085

{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5087

{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5088

{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5092

{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},

arch/powerpc/xmon/ppc-opc.c

5093

{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},

arch/powerpc/xmon/ppc-opc.c

5099

{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5100

{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5102

{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5103

{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5104

{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5105

{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5107

{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5111

{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5112

{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5114

{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5118

{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5119

{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5121

{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5125

{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},

arch/powerpc/xmon/ppc-opc.c

5126

{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},

arch/powerpc/xmon/ppc-opc.c

5127

{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},

arch/powerpc/xmon/ppc-opc.c

5128

{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5132

{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5134

{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5136

{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

5140

{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5141

{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5143

{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5182

{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5184

{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5186

{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5187

{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5189

{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5398

{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5400

{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},

arch/powerpc/xmon/ppc-opc.c

5402

{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5404

{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5409

{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5410

{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5412

{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5420

{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

5422

{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},

arch/powerpc/xmon/ppc-opc.c

5424

{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},

arch/powerpc/xmon/ppc-opc.c

5431

{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5433

{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5434

{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5436

{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5437

{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5438

{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5439

{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5441

{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5442

{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5444

{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5446

{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5450

{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5452

{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5453

{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5455

{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5457

{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5458

{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

546

#define RBS RB + 1

arch/powerpc/xmon/ppc-opc.c

5460

{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5464

{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5466

{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5468

{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5469

{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5470

{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5471

{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5473

{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5477

{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

5479

{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5481

{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5483

{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5495

{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5497

{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5536

{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5541

{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5542

{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5544

{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5545

{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5550

{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5718

{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5720

{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5721

{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5723

{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5725

{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5727

{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5729

{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5734

{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5735

{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5737

{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5738

{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5740

{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5749

{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5753

{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5754

{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5758

{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5759

{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5761

{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5762

{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5763

{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

5764

{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5765

{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5766

{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

5768

{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5769

{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5770

{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5771

{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5773

{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5777

{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5780

{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5782

{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5783

{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5785

{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5787

{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5788

{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5789

{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5790

{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5792

{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5793

{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5798

{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5799

{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5801

{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5802

{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5804

{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5805

{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5807

{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5811

{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5812

{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5814

{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5815

{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

5816

{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5817

{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

5821

{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5828

{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5829

{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5831

{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5835

{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5837

{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5854

{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5856

{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},

arch/powerpc/xmon/ppc-opc.c

5857

{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5859

{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5861

{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5865

{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5870

{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5871

{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5873

{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5877

{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5879

{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5880

{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5882

{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5883

{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5885

{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5889

{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5890

{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5891

{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5892

{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5894

{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5895

{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5896

{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5897

{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5899

{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},

arch/powerpc/xmon/ppc-opc.c

5901

{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5903

{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5904

{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5906

{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5907

{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5909

{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5911

{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5912

{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5914

{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5915

{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5917

{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5918

{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5920

{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5922

{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5923

{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5928

{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5930

{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5935

{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5936

{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5938

{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5942

{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5944

{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5961

{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5963

{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5965

{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5966

{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5968

{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5969

{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5972

{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5974

{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5976

{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5980

{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5987

{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5988

{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5995

{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5996

{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5997

{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5998

{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6006

{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6007

{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6009

{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

6014

{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6016

{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6018

{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6019

{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6020

{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6022

{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6023

{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6025

{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6026

{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6027

{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6028

{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6030

{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6031

{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6033

{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6034

{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6036

{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6038

{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6040

{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6042

{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6044

{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6045

{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6047

{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6048

{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6049

{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6050

{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6052

{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6053

{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6055

{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6057

{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6058

{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6059

{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6061

{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6062

{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6064

{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6066

{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6068

{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6070

{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6074

{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6084

{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6088

{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6089

{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6091

{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6092

{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6096

{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6099

{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},

arch/powerpc/xmon/ppc-opc.c

6100

{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},

arch/powerpc/xmon/ppc-opc.c

6102

{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6109

{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6111

{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6116

{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6117

{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6119

{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6123

{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},

arch/powerpc/xmon/ppc-opc.c

6125

{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6129

{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6134

{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6136

{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6137

{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6139

{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6140

{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6141

{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6142

{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6144

{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6145

{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6149

{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6150

{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6152

{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},

arch/powerpc/xmon/ppc-opc.c

6153

{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},

arch/powerpc/xmon/ppc-opc.c

6155

{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6157

{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6159

{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6160

{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6162

{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6163

{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6165

{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6166

{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6173

{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6175

{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6177

{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6179

{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6181

{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6183

{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6184

{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6185

{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6186

{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6188

{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6189

{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6197

{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6199

{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6200

{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6202

{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6210

{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6215

{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6216

{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6218

{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6219

{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6221

{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6222

{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6224

{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},

arch/powerpc/xmon/ppc-opc.c

6229

{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},

arch/powerpc/xmon/ppc-opc.c

6231

{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6233

{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6235

{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6240

{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6242

{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6244

{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6249

{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6250

{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6252

{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6253

{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6255

{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6259

{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},

arch/powerpc/xmon/ppc-opc.c

6261

{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6263

{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6264

{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6266

{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6268

{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6274

{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},

arch/powerpc/xmon/ppc-opc.c

6275

{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},

arch/powerpc/xmon/ppc-opc.c

6635

{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

7144

{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

7145

{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

7158

{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

7159

{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},

drivers/clk/renesas/r9a06g032-clocks.c

295

D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),

drivers/clk/renesas/r9a06g032-clocks.c

296

RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

297

RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

298

D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),

drivers/clk/renesas/r9a06g032-clocks.c

299

RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

300

RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

301

D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),

drivers/clk/renesas/r9a06g032-clocks.c

302

RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

303

RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

304

D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),

drivers/clk/renesas/r9a06g032-clocks.c

305

RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

306

RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

307

D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),

drivers/clk/renesas/r9a06g032-clocks.c

308

RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

309

RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

310

D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),

drivers/clk/renesas/r9a06g032-clocks.c

311

RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

312

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

313

D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),

drivers/clk/renesas/r9a06g032-clocks.c

314

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

315

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

316

D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),

drivers/clk/renesas/r9a06g032-clocks.c

317

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

318

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

319

D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),

drivers/clk/renesas/r9a06g032-clocks.c

320

RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

321

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

322

D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),

drivers/clk/renesas/r9a06g032-clocks.c

323

RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

324

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

325

D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),

drivers/clk/renesas/r9a06g032-clocks.c

326

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

327

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

328

D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),

drivers/clk/renesas/r9a06g032-clocks.c

329

RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

330

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

331

D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),

drivers/clk/renesas/r9a06g032-clocks.c

332

RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

333

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

334

D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),

drivers/clk/renesas/r9a06g032-clocks.c

335

RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

336

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

337

D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),

drivers/clk/renesas/r9a06g032-clocks.c

338

RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

339

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

340

D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),

drivers/clk/renesas/r9a06g032-clocks.c

341

RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

342

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

343

D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),

drivers/clk/renesas/r9a06g032-clocks.c

344

RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

345

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

346

D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),

drivers/clk/renesas/r9a06g032-clocks.c

347

RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

348

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

349

D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),

drivers/clk/renesas/r9a06g032-clocks.c

350

RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

351

RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

352

D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),

drivers/clk/renesas/r9a06g032-clocks.c

353

RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

354

RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

355

D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),

drivers/clk/renesas/r9a06g032-clocks.c

356

RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

357

RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

358

D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),

drivers/clk/renesas/r9a06g032-clocks.c

359

RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

360

RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

361

D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),

drivers/clk/renesas/r9a06g032-clocks.c

362

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

363

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

364

D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),

drivers/clk/renesas/r9a06g032-clocks.c

365

RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

366

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

367

D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),

drivers/clk/renesas/r9a06g032-clocks.c

368

RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

369

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

370

D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),

drivers/clk/renesas/r9a06g032-clocks.c

371

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

372

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

373

D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),

drivers/clk/renesas/r9a06g032-clocks.c

374

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

375

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

376

D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),

drivers/clk/renesas/r9a06g032-clocks.c

377

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

378

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

379

D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),

drivers/clk/renesas/r9a06g032-clocks.c

380

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

381

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

382

D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),

drivers/clk/renesas/r9a06g032-clocks.c

383

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

384

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

385

D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

386

RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

387

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

388

D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),

drivers/clk/renesas/r9a06g032-clocks.c

389

RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

390

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

391

D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),

drivers/clk/renesas/r9a06g032-clocks.c

392

RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

393

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

394

D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),

drivers/clk/renesas/r9a06g032-clocks.c

395

RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

396

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

397

D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),

drivers/clk/renesas/r9a06g032-clocks.c

398

RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

399

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

400

D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),

drivers/clk/renesas/r9a06g032-clocks.c

401

RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

402

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

403

D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),

drivers/clk/renesas/r9a06g032-clocks.c

404

RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

405

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

406

D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),

drivers/clk/renesas/r9a06g032-clocks.c

407

RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

408

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

410

D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),

drivers/clk/renesas/r9a06g032-clocks.c

411

RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),

drivers/clk/renesas/r9a06g032-clocks.c

412

RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

413

D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),

drivers/clk/renesas/r9a06g032-clocks.c

414

RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

415

RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

416

D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),

drivers/clk/renesas/r9a06g032-clocks.c

417

RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),

drivers/clk/renesas/r9a06g032-clocks.c

418

RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

419

D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),

drivers/clk/renesas/r9a06g032-clocks.c

420

RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

421

RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

422

D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),

drivers/clk/renesas/r9a06g032-clocks.c

423

RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

424

RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

425

D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),

drivers/clk/renesas/r9a06g032-clocks.c

426

RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

427

RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

428

D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),

drivers/clk/renesas/r9a06g032-clocks.c

429

RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

430

RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

431

D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),

drivers/clk/renesas/r9a06g032-clocks.c

432

RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

433

RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

434

D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

435

RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),

drivers/clk/renesas/r9a06g032-clocks.c

436

RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),

drivers/clk/renesas/r9a06g032-clocks.c

437

D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

438

RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),

drivers/clk/renesas/r9a06g032-clocks.c

439

RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

440

D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),

drivers/clk/renesas/r9a06g032-clocks.c

441

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

442

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

443

D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),

drivers/clk/renesas/r9a06g032-clocks.c

444

RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),

drivers/clk/renesas/r9a06g032-clocks.c

445

RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),

drivers/clk/renesas/r9a06g032-clocks.c

446

D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),

drivers/clk/renesas/r9a06g032-clocks.c

447

RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

448

RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

456

D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),

drivers/clk/renesas/r9a06g032-clocks.c

457

RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

458

RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

459

D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),

drivers/clk/renesas/r9a06g032-clocks.c

460

RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

461

RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

462

D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),

drivers/clk/renesas/r9a06g032-clocks.c

463

RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

464

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

465

D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),

drivers/clk/renesas/r9a06g032-clocks.c

466

RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

467

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

468

D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),

drivers/clk/renesas/r9a06g032-clocks.c

469

RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

470

RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

471

D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

472

RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

473

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

474

D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

475

RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

476

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

478

D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),

drivers/clk/renesas/r9a06g032-clocks.c

479

RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),

drivers/clk/renesas/r9a06g032-clocks.c

480

RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

481

D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),

drivers/clk/renesas/r9a06g032-clocks.c

482

RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

483

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

484

D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),

drivers/clk/renesas/r9a06g032-clocks.c

485

RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

486

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

487

D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),

drivers/clk/renesas/r9a06g032-clocks.c

488

RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

489

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

490

D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

491

RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

492

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

493

D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),

drivers/clk/renesas/r9a06g032-clocks.c

494

RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

495

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

496

D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),

drivers/clk/renesas/r9a06g032-clocks.c

497

RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

498

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

499

D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),

drivers/clk/renesas/r9a06g032-clocks.c

500

RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

501

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

502

D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),

drivers/clk/renesas/r9a06g032-clocks.c

503

RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

504

RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

505

D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),

drivers/clk/renesas/r9a06g032-clocks.c

506

RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),

drivers/clk/renesas/r9a06g032-clocks.c

507

RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

508

D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),

drivers/clk/renesas/r9a06g032-clocks.c

509

RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),

drivers/clk/renesas/r9a06g032-clocks.c

510

RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

511

D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

512

RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

513

RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

514

D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),

drivers/clk/renesas/r9a06g032-clocks.c

515

RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),

drivers/clk/renesas/r9a06g032-clocks.c

516

RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),

drivers/clk/renesas/r9a06g032-clocks.c

517

D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

518

RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

519

RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

520

D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),

drivers/clk/renesas/r9a06g032-clocks.c

521

RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),

drivers/clk/renesas/r9a06g032-clocks.c

522

RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

523

D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),

drivers/clk/renesas/r9a06g032-clocks.c

524

RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

525

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

526

D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),

drivers/clk/renesas/r9a06g032-clocks.c

527

RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

528

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

529

D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),

drivers/clk/renesas/r9a06g032-clocks.c

530

RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

531

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

532

D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),

drivers/clk/renesas/r9a06g032-clocks.c

533

RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),

drivers/clk/renesas/r9a06g032-clocks.c

534

RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),

drivers/clk/renesas/r9a06g032-clocks.c

535

D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),

drivers/clk/renesas/r9a06g032-clocks.c

536

RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

537

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

538

D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),

drivers/clk/renesas/r9a06g032-clocks.c

539

RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

540

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

541

D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),

drivers/clk/renesas/r9a06g032-clocks.c

542

RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

543

RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

544

D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),

drivers/clk/renesas/r9a06g032-clocks.c

545

RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

546

RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

547

D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

548

RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

549

RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

550

D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),

drivers/clk/renesas/r9a06g032-clocks.c

551

RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),

drivers/clk/renesas/r9a06g032-clocks.c

552

RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

553

D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),

drivers/clk/renesas/r9a06g032-clocks.c

554

RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),

drivers/clk/renesas/r9a06g032-clocks.c

555

RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),

drivers/clk/renesas/r9a06g032-clocks.c

556

D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),

drivers/clk/renesas/r9a06g032-clocks.c

557

RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

558

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

559

D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),

drivers/clk/renesas/r9a06g032-clocks.c

560

RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

561

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

562

D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),

drivers/clk/renesas/r9a06g032-clocks.c

563

RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

564

RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

565

D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),

drivers/clk/renesas/r9a06g032-clocks.c

566

RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

567

RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

568

D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),

drivers/clk/renesas/r9a06g032-clocks.c

569

RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),

drivers/clk/renesas/r9a06g032-clocks.c

570

RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

571

D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),

drivers/clk/renesas/r9a06g032-clocks.c

572

RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),

drivers/clk/renesas/r9a06g032-clocks.c

573

RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

574

D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),

drivers/clk/renesas/r9a06g032-clocks.c

575

RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

576

RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

577

D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),

drivers/clk/renesas/r9a06g032-clocks.c

578

RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),

drivers/clk/renesas/r9a06g032-clocks.c

579

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

580

D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),

drivers/clk/renesas/r9a06g032-clocks.c

581

RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),

drivers/clk/renesas/r9a06g032-clocks.c

582

RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

583

D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),

drivers/clk/renesas/r9a06g032-clocks.c

584

RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),

drivers/clk/renesas/r9a06g032-clocks.c

585

RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),

drivers/clk/renesas/r9a06g032-clocks.c

586

D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),

drivers/clk/renesas/r9a06g032-clocks.c

587

RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

588

RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

589

D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),

drivers/clk/renesas/r9a06g032-clocks.c

590

RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

591

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

592

D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),

drivers/clk/renesas/r9a06g032-clocks.c

593

RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

594

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

595

D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),

drivers/clk/renesas/r9a06g032-clocks.c

596

RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

597

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

598

D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),

drivers/clk/renesas/r9a06g032-clocks.c

599

RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

600

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

601

D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),

drivers/clk/renesas/r9a06g032-clocks.c

602

RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

603

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

604

D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),

drivers/clk/renesas/r9a06g032-clocks.c

605

RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

606

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

607

D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),

drivers/clk/renesas/r9a06g032-clocks.c

608

RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

609

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

610

D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),

drivers/clk/renesas/r9a06g032-clocks.c

611

RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

612

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

613

D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),

drivers/clk/renesas/r9a06g032-clocks.c

614

RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

615

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

616

D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),

drivers/clk/renesas/r9a06g032-clocks.c

617

RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

618

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

619

D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),

drivers/clk/renesas/r9a06g032-clocks.c

620

RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

621

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

622

D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),

drivers/clk/renesas/r9a06g032-clocks.c

623

RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

624

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

625

D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),

drivers/clk/renesas/r9a06g032-clocks.c

626

RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

627

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

628

D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),

drivers/clk/renesas/r9a06g032-clocks.c

629

RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

630

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

631

D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),

drivers/clk/renesas/r9a06g032-clocks.c

632

RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

633

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

634

D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),

drivers/clk/renesas/r9a06g032-clocks.c

635

RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),

drivers/clk/renesas/r9a06g032-clocks.c

636

RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),

drivers/clk/renesas/r9a06g032-clocks.c

648

.dual.sel = RB(0x34, 30),

drivers/clk/renesas/r9a06g032-clocks.c

657

.dual.sel = RB(0xec, 24),

drivers/clk/renesas/r9a06g032-clocks.c

661

RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),

drivers/clk/renesas/r9a06g032-clocks.c

663

RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),

drivers/clk/renesas/r9a06g032-clocks.c

665

RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),

drivers/clk/renesas/r9a06g032-clocks.c

667

RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),

drivers/clk/renesas/r9a06g032-clocks.c

669

RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),

drivers/clk/renesas/r9a06g032-clocks.c

671

RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),

drivers/clk/renesas/r9a06g032-clocks.c

673

RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),

drivers/clk/renesas/r9a06g032-clocks.c

675

RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),

drivers/clocksource/timer-atmel-tcb.c

97

writel(0, tcaddr + ATMEL_TC_REG(i, RB));

drivers/counter/microchip-tcb-capture.c

268

ret = regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), &cnt);

drivers/counter/microchip-tcb-capture.c

296

ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), val);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

920

modifier |= AMD_FMT_MOD_SET(RB, rb) |

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

988

return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

505

AMD_FMT_MOD_SET(RB, rb) |

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

519

AMD_FMT_MOD_SET(RB, rb) |

drivers/media/platform/rockchip/rga/rga-hw.c

107

case RB:

drivers/media/platform/rockchip/rga/rga-hw.c

84

LT, RT, LB, RB,

drivers/media/platform/rockchip/rga/rga-hw.c

87

RT, LT, RB, LB,

drivers/media/platform/rockchip/rga/rga-hw.c

90

RB, LB, RT, LT,

drivers/media/platform/rockchip/rga/rga-hw.c

93

LB, RB, LT, RT,

drivers/net/wireless/ath/carl9170/main.c

1538

BUILD_BUG_ON(RB > CARL9170_MAX_CMD_PAYLOAD_LEN);

drivers/net/wireless/ath/carl9170/main.c

1546

RB, (u8 *) rng_load,

drivers/net/wireless/ath/carl9170/main.c

1547

RB, (u8 *) buf);

drivers/net/wireless/ath/carl9170/main.c

1859

BUILD_BUG_ON(RB > CARL9170_MAX_CMD_LEN - 4);

drivers/net/wireless/ath/carl9170/main.c

1862

BUILD_BUG_ON(sizeof(ar->eeprom) % RB);

drivers/net/wireless/ath/carl9170/main.c

1865

for (i = 0; i < sizeof(ar->eeprom) / RB; i++) {

drivers/net/wireless/ath/carl9170/main.c

1868

RB * i + 4 * j);

drivers/net/wireless/ath/carl9170/main.c

1871

RB, (u8 *) &offsets,

drivers/net/wireless/ath/carl9170/main.c

1872

RB, eeprom + RB * i);

drivers/pwm/pwm-atmel-tcb.c

245

ATMEL_TC_REG(tcbpwmc->channel, RB),

drivers/pwm/pwm-atmel-tcb.c

494

regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);

drivers/pwm/pwm-atmel-tcb.c

509

regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), chan->rb);

drivers/pwm/pwm-atmel-tcb.c

98

ATMEL_TC_REG(tcbpwmc->channel, RB),

tools/testing/selftests/powerpc/include/instructions.h

10

(0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))

tools/testing/selftests/powerpc/include/instructions.h

11

#define COPY(RA, RB, L) \

tools/testing/selftests/powerpc/include/instructions.h

12

.long __COPY((RA), (RB), (L))

tools/testing/selftests/powerpc/include/instructions.h

33

#define __PASTE(RA, RB, L, RC) \

tools/testing/selftests/powerpc/include/instructions.h

34

(0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))

tools/testing/selftests/powerpc/include/instructions.h

35

#define PASTE(RA, RB, L, RC) \

tools/testing/selftests/powerpc/include/instructions.h

36

.long __PASTE((RA), (RB), (L), (RC))

tools/testing/selftests/powerpc/include/instructions.h

9

#define __COPY(RA, RB, L) \