arch/powerpc/xmon/ppc-opc.c
3037
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3038
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3039
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3040
{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3041
{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3042
{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3043
{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3044
{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3045
{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3046
{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3047
{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3048
{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3049
{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3050
{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3051
{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3052
{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3054
{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3055
{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3056
{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3057
{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3058
{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3059
{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3060
{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3061
{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3062
{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3063
{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3064
{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3065
{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3066
{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3067
{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3068
{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3069
{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3070
{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3071
{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3072
{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3073
{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3074
{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3075
{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3076
{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3077
{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3078
{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3079
{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3080
{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3081
{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3082
{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3083
{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3084
{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3085
{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3096
{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
arch/powerpc/xmon/ppc-opc.c
3098
{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
arch/powerpc/xmon/ppc-opc.c
3100
{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3101
{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3107
{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3109
{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3141
{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3143
{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3146
{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3171
{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
arch/powerpc/xmon/ppc-opc.c
3173
{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
arch/powerpc/xmon/ppc-opc.c
3176
{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3178
{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3179
{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3180
{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3181
{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3182
{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3196
{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3197
{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3206
{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3207
{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3208
{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3209
{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3219
{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3221
{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3222
{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3223
{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3232
{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3233
{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3234
{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3235
{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3236
{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3237
{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3247
{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3248
{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3255
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3256
{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3257
{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3258
{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3259
{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3264
{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3265
{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
3270
{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3272
{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3273
{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3275
{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3276
{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3279
{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3280
{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3282
{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3285
{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3286
{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3287
{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3288
{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
arch/powerpc/xmon/ppc-opc.c
3289
{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3290
{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3291
{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
arch/powerpc/xmon/ppc-opc.c
3293
{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3294
{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3295
{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3296
{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3297
{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3298
{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3299
{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3300
{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3301
{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3302
{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3304
{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3306
{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3307
{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3308
{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3309
{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3310
{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3311
{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3312
{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3313
{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3314
{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3327
{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
arch/powerpc/xmon/ppc-opc.c
3329
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3331
{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3333
{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3335
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3336
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3339
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3340
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3342
{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3345
{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3346
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3357
{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
arch/powerpc/xmon/ppc-opc.c
3359
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3360
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3361
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3362
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
arch/powerpc/xmon/ppc-opc.c
3363
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3364
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3366
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3368
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3369
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3372
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3373
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3375
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3377
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3378
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3390
{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
arch/powerpc/xmon/ppc-opc.c
3392
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3393
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3394
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3395
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3396
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3399
{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3400
{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3401
{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3402
{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3403
{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3406
{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3407
{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3408
{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3419
{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
arch/powerpc/xmon/ppc-opc.c
3421
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3422
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3423
{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3424
{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3426
{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3427
{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3429
{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3430
{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3432
{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3434
{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3436
{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3439
{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3442
{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3443
{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3445
{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3446
{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3447
{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3448
{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3449
{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3450
{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3451
{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3452
{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3453
{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3454
{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3455
{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3456
{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3457
{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3458
{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3459
{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3460
{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3461
{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3462
{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3463
{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3464
{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3465
{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3466
{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3467
{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3468
{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3469
{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3470
{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3471
{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3472
{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3473
{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3485
{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3486
{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3487
{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3488
{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3489
{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3490
{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3500
{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3501
{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3510
{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3511
{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3512
{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3513
{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3518
{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3524
{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3526
{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3527
{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3529
{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3530
{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3532
{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3533
{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3534
{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3535
{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3538
{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3539
{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3540
{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3541
{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3542
{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3543
{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3544
{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3545
{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3555
{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3557
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3559
{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3561
{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3563
{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3564
{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3565
{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3566
{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3567
{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3568
{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3569
{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3570
{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3571
{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3574
{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3575
{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3576
{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3577
{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3578
{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3579
{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3580
{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3581
{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3582
{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3594
{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3595
{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3599
{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3601
{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3602
{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3603
{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3604
{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3606
{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3611
{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3613
{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3614
{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3615
{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3616
{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3618
{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3619
{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3620
{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3621
{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3625
{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3627
{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3629
{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3630
{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3633
{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3637
{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3638
{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3641
{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3642
{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3644
{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3645
{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3646
{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3647
{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3648
{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3649
{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3650
{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3651
{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3652
{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3653
{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3654
{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3656
{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3658
{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3665
{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3667
{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3670
{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3671
{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3672
{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3673
{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3674
{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3675
{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3676
{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3677
{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3678
{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3680
{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3689
{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3691
{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3692
{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3696
{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3697
{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3698
{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3699
{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3700
{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3701
{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3702
{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3703
{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3704
{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3705
{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3706
{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3707
{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3708
{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3709
{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3710
{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3711
{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3713
{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3719
{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3720
{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3723
{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3724
{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3725
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3726
{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3727
{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3728
{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3729
{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3730
{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3753
{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3760
{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3770
{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3786
{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3787
{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3788
{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3794
{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3797
{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3798
{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3799
{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3800
{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3809
{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3810
{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3811
{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3818
{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3819
{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3820
{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3821
{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3822
{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3824
{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3825
{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3827
{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3828
{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3830
{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3832
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3833
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3834
{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3835
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3837
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3838
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3839
{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3840
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3842
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3843
{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3844
{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
3846
{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3847
{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3848
{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
4586
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4587
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4589
{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4590
{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4592
{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
4593
{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
arch/powerpc/xmon/ppc-opc.c
4594
{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4595
{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4596
{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
4597
{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
arch/powerpc/xmon/ppc-opc.c
4598
{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4599
{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4601
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4602
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4604
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4605
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4606
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4607
{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4608
{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4609
{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
4612
{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4613
{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4615
{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4616
{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4619
{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4620
{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4622
{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4623
{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4625
{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4626
{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4628
{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4629
{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
arch/powerpc/xmon/ppc-opc.c
4631
{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
4632
{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
arch/powerpc/xmon/ppc-opc.c
4633
{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4634
{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
4635
{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
arch/powerpc/xmon/ppc-opc.c
4636
{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4638
{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
arch/powerpc/xmon/ppc-opc.c
4639
{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
arch/powerpc/xmon/ppc-opc.c
4641
{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4642
{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4644
{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4645
{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
arch/powerpc/xmon/ppc-opc.c
4647
{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4648
{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
arch/powerpc/xmon/ppc-opc.c
4649
{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4650
{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
arch/powerpc/xmon/ppc-opc.c
4652
{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
arch/powerpc/xmon/ppc-opc.c
4653
{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
arch/powerpc/xmon/ppc-opc.c
4655
{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4656
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4657
{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4658
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4660
{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4661
{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4662
{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4663
{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4664
{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4665
{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4666
{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4667
{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4668
{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4669
{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4670
{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4671
{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4672
{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4673
{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4674
{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4675
{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4676
{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4677
{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4678
{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4679
{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4680
{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4681
{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4682
{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4683
{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4684
{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4685
{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4686
{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4687
{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4689
{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4690
{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4691
{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4692
{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4696
{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4698
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4699
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4700
{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4701
{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4702
{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4703
{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4705
{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4706
{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4708
{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4709
{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4710
{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4711
{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4713
{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4714
{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4735
{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4737
{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4738
{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4739
{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4740
{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4742
{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4743
{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4744
{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4745
{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4747
{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4748
{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4750
{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4751
{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4753
{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4754
{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4763
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4764
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4765
{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4766
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4770
{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4772
{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4778
{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4786
{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4787
{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4788
{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4789
{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4791
{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
arch/powerpc/xmon/ppc-opc.c
4792
{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
arch/powerpc/xmon/ppc-opc.c
4793
{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
arch/powerpc/xmon/ppc-opc.c
4794
{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4803
{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4805
{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4806
{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4808
{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4809
{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4817
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4818
{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4819
{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4820
{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4821
{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4822
{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4823
{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4824
{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4825
{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4826
{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4827
{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4828
{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4829
{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4830
{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4831
{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4832
{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4834
{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4835
{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4836
{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4838
{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4839
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4841
{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4842
{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4860
{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4862
{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4863
{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4865
{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4866
{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4868
{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4872
{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
arch/powerpc/xmon/ppc-opc.c
4873
{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
arch/powerpc/xmon/ppc-opc.c
4874
{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
arch/powerpc/xmon/ppc-opc.c
4878
{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4882
{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4884
{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
arch/powerpc/xmon/ppc-opc.c
4885
{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4886
{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
arch/powerpc/xmon/ppc-opc.c
4887
{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4898
{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4900
{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4901
{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4902
{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4903
{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4905
{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4906
{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4907
{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4908
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4931
{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4933
{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4934
{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4936
{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4937
{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
4939
{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4950
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4952
{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
arch/powerpc/xmon/ppc-opc.c
4959
{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
arch/powerpc/xmon/ppc-opc.c
4960
{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
arch/powerpc/xmon/ppc-opc.c
4961
{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
arch/powerpc/xmon/ppc-opc.c
4962
{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
arch/powerpc/xmon/ppc-opc.c
4972
{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
4973
{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
4975
{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
4977
{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4982
{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4984
{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4985
{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4986
{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4987
{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4989
{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4990
{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4991
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4992
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4998
{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
arch/powerpc/xmon/ppc-opc.c
4999
{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
arch/powerpc/xmon/ppc-opc.c
5000
{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
arch/powerpc/xmon/ppc-opc.c
5001
{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
arch/powerpc/xmon/ppc-opc.c
5009
{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5010
{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5012
{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5013
{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5017
{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5022
{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5024
{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5025
{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5026
{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5027
{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5029
{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5030
{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5032
{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5033
{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5034
{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5035
{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5037
{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5038
{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5039
{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5040
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5042
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5047
{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
arch/powerpc/xmon/ppc-opc.c
5048
{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
arch/powerpc/xmon/ppc-opc.c
5049
{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
arch/powerpc/xmon/ppc-opc.c
5058
{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
5059
{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
5061
{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5065
{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
5066
{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
507
#define RA0 RA + 1
arch/powerpc/xmon/ppc-opc.c
5070
{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5074
{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5075
{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5076
{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5078
{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5080
{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5081
{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5082
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5083
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5085
{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5095
{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5099
{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5100
{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5109
{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5111
{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5112
{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5116
{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
5130
{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
arch/powerpc/xmon/ppc-opc.c
5138
{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5140
{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5141
{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5186
{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5187
{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5400
{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
arch/powerpc/xmon/ppc-opc.c
5406
{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5407
{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5409
{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5410
{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5422
{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
arch/powerpc/xmon/ppc-opc.c
5426
{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5428
{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5429
{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5434
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5436
{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5437
{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5438
{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5439
{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5444
{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5448
{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
arch/powerpc/xmon/ppc-opc.c
5452
{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5453
{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5457
{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5458
{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5462
{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5468
{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5469
{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5470
{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5471
{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5494
{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
arch/powerpc/xmon/ppc-opc.c
5495
{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5496
{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
arch/powerpc/xmon/ppc-opc.c
5497
{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5541
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5542
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5544
{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5545
{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5720
{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5721
{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5723
{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5731
{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5732
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5734
{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5735
{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5737
{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5738
{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5740
{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5745
{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5747
{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5749
{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5753
{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5754
{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5759
{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5761
{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5762
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5763
{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5764
{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5765
{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5766
{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5768
{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5769
{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5770
{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5771
{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5775
{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5780
{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5783
{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5787
{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5788
{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5789
{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5790
{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5792
{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5793
{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5795
{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5796
{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5798
{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5799
{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5801
{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5802
{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5804
{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5805
{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5812
{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5814
{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5815
{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5816
{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5817
{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5823
{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5824
{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
5828
{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5829
{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5835
{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5859
{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5865
{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5867
{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5868
{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5870
{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5871
{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5873
{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5875
{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
5879
{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5880
{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5883
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5889
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5890
{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5891
{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5892
{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5894
{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5895
{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5896
{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5897
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5911
{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5912
{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5914
{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5915
{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5917
{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5918
{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5923
{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5932
{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
5933
{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
5935
{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5936
{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5942
{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5948
{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5949
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5950
{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5951
{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5953
{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5954
{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5955
{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5956
{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5965
{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5966
{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5968
{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5969
{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
5974
{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5980
{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5982
{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5983
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5984
{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5985
{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5987
{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5988
{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5990
{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5991
{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5992
{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5993
{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5995
{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5996
{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5997
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5998
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6011
{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6012
{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6020
{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6022
{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6023
{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6025
{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6026
{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6027
{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6028
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6030
{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6031
{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6036
{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6045
{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6047
{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6048
{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6049
{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6050
{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6052
{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6053
{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6055
{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6064
{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6066
{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6074
{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6076
{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6077
{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6078
{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6079
{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6081
{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
6082
{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
6088
{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6089
{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6094
{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
arch/powerpc/xmon/ppc-opc.c
6113
{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6114
{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6116
{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6117
{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6121
{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
arch/powerpc/xmon/ppc-opc.c
6131
{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
6132
{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
arch/powerpc/xmon/ppc-opc.c
6137
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6139
{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6140
{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6141
{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6142
{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6147
{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
arch/powerpc/xmon/ppc-opc.c
6162
{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6163
{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6165
{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6166
{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
6168
{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6169
{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6170
{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6171
{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6173
{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6183
{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6184
{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6185
{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6186
{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6191
{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
arch/powerpc/xmon/ppc-opc.c
6193
{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6194
{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6199
{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6200
{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6202
{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6204
{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6205
{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
6207
{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6208
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6215
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6216
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6218
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6219
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6225
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6226
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6237
{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6238
{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
arch/powerpc/xmon/ppc-opc.c
6246
{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6247
{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6249
{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6250
{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6252
{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6253
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6274
{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
arch/powerpc/xmon/ppc-opc.c
6275
{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
arch/powerpc/xmon/ppc-opc.c
6338
{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
arch/powerpc/xmon/ppc-opc.c
6344
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
arch/powerpc/xmon/ppc-opc.c
6635
{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6661
{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
arch/powerpc/xmon/ppc-opc.c
6662
{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
arch/powerpc/xmon/ppc-opc.c
6669
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
arch/powerpc/xmon/ppc-opc.c
6670
{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
arch/powerpc/xmon/ppc-opc.c
7010
{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7011
{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7012
{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7013
{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7014
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7015
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7016
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7017
{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7018
{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7019
{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7020
{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7021
{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7022
{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7023
{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7024
{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7025
{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7027
{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7028
{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7029
{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7030
{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7050
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
7052
{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
7094
{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
arch/powerpc/xmon/ppc-opc.c
7095
{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
arch/powerpc/xmon/ppc-opc.c
7096
{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
arch/powerpc/xmon/ppc-opc.c
7097
{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
arch/powerpc/xmon/ppc-opc.c
7098
{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
arch/powerpc/xmon/ppc-opc.c
7099
{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
arch/powerpc/xmon/ppc-opc.c
7100
{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
arch/powerpc/xmon/ppc-opc.c
7101
{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
arch/powerpc/xmon/ppc-opc.c
7102
{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
arch/powerpc/xmon/ppc-opc.c
7104
{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
arch/powerpc/xmon/ppc-opc.c
7105
{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
arch/powerpc/xmon/ppc-opc.c
7144
{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
7145
{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
7153
{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
7154
{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
7158
{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
7159
{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
arch/powerpc/xmon/ppc-opc.c
7164
{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
7165
{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
7174
{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
arch/powerpc/xmon/ppc-opc.c
7175
{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
drivers/clocksource/timer-atmel-tcb.c
322
writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
drivers/clocksource/timer-atmel-tcb.c
96
writel(0, tcaddr + ATMEL_TC_REG(i, RA));
drivers/counter/microchip-tcb-capture.c
265
ret = regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), &cnt);
drivers/counter/microchip-tcb-capture.c
293
ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), val);
drivers/media/platform/chips-media/coda/coda-gdi.c
100
RBC(RA, 8, RA, 9),
drivers/media/platform/chips-media/coda/coda-gdi.c
101
RBC(RA, 9, RA, 10),
drivers/media/platform/chips-media/coda/coda-gdi.c
102
RBC(RA, 10, RA, 11),
drivers/media/platform/chips-media/coda/coda-gdi.c
103
RBC(RA, 11, RA, 12),
drivers/media/platform/chips-media/coda/coda-gdi.c
104
RBC(RA, 12, RA, 13),
drivers/media/platform/chips-media/coda/coda-gdi.c
105
RBC(RA, 13, RA, 14),
drivers/media/platform/chips-media/coda/coda-gdi.c
106
RBC(RA, 14, RA, 15),
drivers/media/platform/chips-media/coda/coda-gdi.c
107
RBC(RA, 15, ZERO, 0),
drivers/media/platform/chips-media/coda/coda-gdi.c
91
RBC(CA, 15, RA, 0),
drivers/media/platform/chips-media/coda/coda-gdi.c
92
RBC(RA, 0, RA, 1),
drivers/media/platform/chips-media/coda/coda-gdi.c
93
RBC(RA, 1, RA, 2),
drivers/media/platform/chips-media/coda/coda-gdi.c
94
RBC(RA, 2, RA, 3),
drivers/media/platform/chips-media/coda/coda-gdi.c
95
RBC(RA, 3, RA, 4),
drivers/media/platform/chips-media/coda/coda-gdi.c
96
RBC(RA, 4, RA, 5),
drivers/media/platform/chips-media/coda/coda-gdi.c
97
RBC(RA, 5, RA, 6),
drivers/media/platform/chips-media/coda/coda-gdi.c
98
RBC(RA, 6, RA, 7),
drivers/media/platform/chips-media/coda/coda-gdi.c
99
RBC(RA, 7, RA, 8),
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
1286
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
1297
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
771
REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2),
drivers/net/ethernet/intel/e1000/e1000_hw.c
4278
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
drivers/net/ethernet/intel/e1000/e1000_hw.c
4280
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
drivers/net/ethernet/intel/e1000/e1000_hw.c
4366
E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
drivers/net/ethernet/intel/e1000/e1000_hw.c
4368
E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
drivers/net/ethernet/intel/e1000/e1000_main.c
2310
E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
drivers/net/ethernet/intel/e1000/e1000_main.c
2312
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
1977
MCU_WM_UNI_CMD(RA), true);
drivers/pwm/pwm-atmel-tcb.c
241
ATMEL_TC_REG(tcbpwmc->channel, RA),
drivers/pwm/pwm-atmel-tcb.c
493
regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
drivers/pwm/pwm-atmel-tcb.c
508
regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
drivers/pwm/pwm-atmel-tcb.c
94
ATMEL_TC_REG(tcbpwmc->channel, RA),
tools/testing/selftests/powerpc/include/instructions.h
10
(0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
tools/testing/selftests/powerpc/include/instructions.h
11
#define COPY(RA, RB, L) \
tools/testing/selftests/powerpc/include/instructions.h
12
.long __COPY((RA), (RB), (L))
tools/testing/selftests/powerpc/include/instructions.h
33
#define __PASTE(RA, RB, L, RC) \
tools/testing/selftests/powerpc/include/instructions.h
34
(0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
tools/testing/selftests/powerpc/include/instructions.h
35
#define PASTE(RA, RB, L, RC) \
tools/testing/selftests/powerpc/include/instructions.h
36
.long __PASTE((RA), (RB), (L), (RC))
tools/testing/selftests/powerpc/include/instructions.h
9
#define __COPY(RA, RB, L) \
