PWM
LUTON_P(29, PWM, NONE);
SERVAL_P(5, PWM, NONE, NONE);
OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
JAGUAR2_P(23, PWM, NONE);
SERVALT_P(17, PWM, NONE, TWI_SCL_M);
SPARX5_P(23, PWM, UART3, TWI_SCL_M);
SPARX5_P(30, SG2, SI, PWM);
FUNCTION_GROUP(pwm, PWM), \
PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0),
TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0),
TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0),
TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0),
TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0),
TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0),
TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0),
MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;