Symbol: PUSH_MTHD
drivers/gpu/drm/nouveau/dispnv50/base507c.c
127
PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
141
PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
167
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
180
PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
204
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
217
PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
44
PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
57
PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
61
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
74
PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
78
PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
81
PUSH_MTHD(push, NV507C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
88
PUSH_MTHD(push, NV507C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base507c.c
96
PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/base507c.c
98
PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
drivers/gpu/drm/nouveau/dispnv50/base827c.c
37
PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
41
PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/base827c.c
44
PUSH_MTHD(push, NV827C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
51
PUSH_MTHD(push, NV827C, SET_PROCESSING,
drivers/gpu/drm/nouveau/dispnv50/base827c.c
59
PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
102
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
165
PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
179
PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
37
PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
42
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
44
PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
74
PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
77
PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/base907c.c
80
PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/base907c.c
93
PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
139
PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
43
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
49
PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |
drivers/gpu/drm/nouveau/dispnv50/core507d.c
90
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/core507d.c
95
PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/core507d.c
97
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
137
PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
140
PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
149
PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
44
PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
61
PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
67
PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
69
PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/corec37d.c
74
PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
40
PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
43
PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/corec57d.c
51
PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
29
PUSH_MTHD(push, NVCA7D, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
36
PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
41
PUSH_MTHD(push, NVCA7D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
44
PUSH_MTHD(push, NVCA7D, UPDATE,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
50
PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
69
PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
77
PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
87
PUSH_MTHD(push, NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
93
PUSH_MTHD(push, NVCA7D, HEAD_SET_TILE_MASK(i), BIT(i));
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
95
PUSH_MTHD(push, NVCA7D, TILE_SET_TILE_SIZE(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
64
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
65
PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
67
PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
68
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crc907d.c
84
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
44
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
45
PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
47
PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
48
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c
63
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
40
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
41
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
43
PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcc57d.c
44
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
28
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CRC(i), crc_hi,
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
35
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
55
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i), 0);
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
79
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/dac507d.c
44
PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
drivers/gpu/drm/nouveau/dispnv50/dac907d.c
38
PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
118
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
132
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
149
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
198
PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head507d.c
212
PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
215
PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
233
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
288
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
303
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
356
PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
365
PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
39
PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
393
PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
410
PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
416
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
420
PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
58
PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
90
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
104
PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
120
PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
123
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
137
PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
145
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
39
PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
44
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
58
PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
69
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/head827d.c
83
PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
drivers/gpu/drm/nouveau/dispnv50/head827d.c
86
PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
120
PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
148
PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
162
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
167
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
181
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
191
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
205
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
219
PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
222
PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
240
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
256
PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
259
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
273
PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
281
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
drivers/gpu/drm/nouveau/dispnv50/head907d.c
333
PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
358
PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
363
PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
388
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
394
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
398
PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
46
PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
67
PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
87
PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head917d.c
40
PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/head917d.c
73
PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
drivers/gpu/drm/nouveau/dispnv50/head917d.c
88
PUSH_MTHD(push, NV917D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/head917d.c
98
PUSH_MTHD(push, NV917D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
114
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
118
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
132
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
148
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
149
PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
171
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
185
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
220
PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
240
PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
243
PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
247
PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
264
PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
268
PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
55
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
74
PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
95
PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
106
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
120
PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
212
PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
232
PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
235
PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
239
PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
68
PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
89
PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
100
PUSH_MTHD(push, NVCA7D, HEAD_SET_DITHER_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
121
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
125
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
144
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(i, 0), curs_hi);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
146
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
151
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
180
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
199
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_OLUT(i), olut_hi,
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
206
PUSH_MTHD(push, NVCA7D, HEAD_SET_OLUT_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
229
PUSH_MTHD(push, NVCA7D, HEAD_SET_RASTER_SIZE(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
24
PUSH_MTHD(push, NVCA7D, HEAD_SET_DISPLAY_ID(i, 0), display_id);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
245
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
248
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
251
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
268
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
272
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
59
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
81
PUSH_MTHD(push, NVCA7D, HEAD_SET_PROCAMP(i),
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
42
PUSH_MTHD(push, NV507E, SET_POINT_IN,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
64
PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
68
PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
70
PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
73
PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
75
PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
41
PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
45
PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
47
PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
50
PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
52
PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
38
PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
42
PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
44
PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
47
PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
49
PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/pior507d.c
45
PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sor507d.c
45
PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sor907d.c
41
PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/sorc37d.c
38
PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
40
PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
55
PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
104
PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
149
PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
153
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
166
PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
171
PUSH_MTHD(push, NVC37E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
193
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
194
PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
196
PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
200
PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
204
PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
219
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
232
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
249
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
262
PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset,
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
278
PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
282
PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
49
PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
62
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
75
PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
108
PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
121
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
134
PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
41
PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
46
PUSH_MTHD(push, NVC57E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
64
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
65
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
67
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
71
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
75
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
95
PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
38
PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
43
PUSH_MTHD(push, NVC57E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
60
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
61
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
63
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
67
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
71
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
106
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
124
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ILUT, ilut_hi,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
131
PUSH_MTHD(push, NVCA7E, SET_ILUT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
149
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
169
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
176
PUSH_MTHD(push, NVCA7E, SET_NOTIFIER_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
24
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
28
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
51
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ISO(0), iso0_hi);
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
53
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
59
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
64
PUSH_MTHD(push, NVCA7E, SET_SIZE,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
81
PUSH_MTHD(push, NVCA7E, SET_POINT_IN(0),
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
85
PUSH_MTHD(push, NVCA7E, SET_SIZE_IN,
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
89
PUSH_MTHD(push, NVCA7E, SET_SIZE_OUT,
drivers/gpu/drm/nouveau/gv100_fence.c
25
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
drivers/gpu/drm/nouveau/gv100_fence.c
29
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
drivers/gpu/drm/nouveau/gv100_fence.c
35
PUSH_MTHD(push, NVC36F, MEM_OP_A, 0,
drivers/gpu/drm/nouveau/gv100_fence.c
40
PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
drivers/gpu/drm/nouveau/gv100_fence.c
56
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
drivers/gpu/drm/nouveau/gv100_fence.c
60
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
drivers/gpu/drm/nouveau/nouveau_bo0039.c
106
PUSH_MTHD(push, NV039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
107
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->cli->drm->ntfy.handle);
drivers/gpu/drm/nouveau/nouveau_bo0039.c
62
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
drivers/gpu/drm/nouveau/nouveau_bo0039.c
73
PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
drivers/gpu/drm/nouveau/nouveau_bo0039.c
86
PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
102
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
106
PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
112
PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
drivers/gpu/drm/nouveau/nouveau_bo5039.c
126
PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
146
PUSH_MTHD(push, NV5039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_bo5039.c
147
PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->cli->drm->ntfy.handle,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
63
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
80
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo5039.c
85
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
56
PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
61
PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
70
PUSH_MTHD(push, NV9039, LAUNCH_DMA,
drivers/gpu/drm/nouveau/nouveau_bo9039.c
96
PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
drivers/gpu/drm/nouveau/nouveau_boa0b5.c
49
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_dmem.c
600
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
drivers/gpu/drm/nouveau/nouveau_dmem.c
614
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
drivers/gpu/drm/nouveau/nouveau_dmem.c
654
PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
drivers/gpu/drm/nouveau/nouveau_dmem.c
663
PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
drivers/gpu/drm/nouveau/nouveau_dmem.c
668
PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
drivers/gpu/drm/nouveau/nouveau_dmem.c
670
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
drivers/gpu/drm/nouveau/nv10_fence.c
38
PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
drivers/gpu/drm/nouveau/nv17_fence.c
57
PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
drivers/gpu/drm/nouveau/nv17_fence.c
65
PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
drivers/gpu/drm/nouveau/nv84_fence.c
41
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
drivers/gpu/drm/nouveau/nv84_fence.c
43
PUSH_MTHD(push, NV826F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nv84_fence.c
64
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
drivers/gpu/drm/nouveau/nv84_fence.c
66
PUSH_MTHD(push, NV826F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvc0_fence.c
40
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvc0_fence.c
63
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvif/chan906f.c
31
PUSH_MTHD(push, NV906F, SEMAPHOREA,
drivers/gpu/drm/nouveau/nvif/chanc36f.c
36
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(addr),
drivers/gpu/drm/nouveau/nvif/chanc36f.c
42
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,