arch/x86/events/intel/cstate.c

181

[PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &group_cstate_core_c7, test_msr },

arch/x86/events/intel/cstate.c

452

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

463

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

478

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

491

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

513

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

525

BIT(PERF_CSTATE_CORE_C7_RES),

arch/x86/events/intel/cstate.c

535

BIT(PERF_CSTATE_CORE_C7_RES),