arch/x86/events/intel/cstate.c

180

[PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &group_cstate_core_c6, test_msr },

arch/x86/events/intel/cstate.c

442

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

451

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

462

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

477

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

490

.core_events = BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

504

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

512

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

524

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

534

BIT(PERF_CSTATE_CORE_C6_RES) |

arch/x86/events/intel/cstate.c

546

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

554

.core_events = BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

566

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

576

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

583

BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c

688

pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;