PCI_ROM_ADDRESS
case PCI_ROM_ADDRESS:
case PCI_ROM_ADDRESS:
case PCI_ROM_ADDRESS:
case PCI_ROM_ADDRESS:
case PCI_ROM_ADDRESS:
dev->rom_base_reg = PCI_ROM_ADDRESS;
if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
dev->rom_base_reg = PCI_ROM_ADDRESS;
if (where == PCI_ROM_ADDRESS)
if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) &&
case PCI_ROM_ADDRESS:
memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
[PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff,
ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
pci_write_config_dword(parent, PCI_ROM_ADDRESS, ddata->bridge_pci_data.rom_addreess);
pci_read_config_dword(parent, PCI_ROM_ADDRESS, &ddata->bridge_pci_data.rom_addreess);
PCI_ROM_ADDRESS) {
} else if (where >= PCI_ROM_ADDRESS && where + size <=
PCI_ROM_ADDRESS, temp_dword);
pci_bus_write_config_dword(ibmphp_pci_bus, devfn, PCI_ROM_ADDRESS, 0x00L);
pci_read_bases(dev, PCI_STD_NUM_BARS, PCI_ROM_ADDRESS);
vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
(offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
pci_write_config_dword(pd, PCI_ROM_ADDRESS, rom_base | PCI_ROM_ADDRESS_ENABLE);
if (offs != PCI_ROM_ADDRESS &&
pci_write_config_dword(sti->pd, PCI_ROM_ADDRESS, rom_base & ~PCI_ROM_ADDRESS_ENABLE);
if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
CFG_FIELD_ROM(PCI_ROM_ADDRESS),