PCI_PRIMARY_BUS
out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
if ((offset == PCI_PRIMARY_BUS) &&
case PCI_PRIMARY_BUS:
pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus);
pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS,
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
case PCI_PRIMARY_BUS: {
u32 val = le32_to_cpu(cfgspace[PCI_PRIMARY_BUS / 4]);
case PCI_PRIMARY_BUS:
if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
pci_read_config_dword(bus->self, PCI_PRIMARY_BUS, &buses);
pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses);
PCI_PRIMARY_BUS, &work);
rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_PRIMARY_BUS, func->bus);
pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, func->busno);
bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
[PCI_PRIMARY_BUS / 4] = {
pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
pci_write_config_dword(dev, PCI_PRIMARY_BUS,
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);
pci_write_config_dword(dev, PCI_PRIMARY_BUS,
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
config_writel(socket, PCI_PRIMARY_BUS,