PCI_MEMORY_BASE
pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
case PCI_MEMORY_BASE:
pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16);
case PCI_MEMORY_BASE:
writel(0x0000fff0, base + PCI_MEMORY_BASE);
rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0x0000 | bus->rangeMem->start >> 16);
pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0xffff);
pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &start_mem_address);
[PCI_MEMORY_BASE / 4] = {
pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);