PCI_CLASS_BRIDGE_PCI_NORMAL
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1);
.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
*val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
dev_rev |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
pdev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
class |= PCI_CLASS_BRIDGE_PCI_NORMAL;
val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
{PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL, ~0)},
cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
{ PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL, ~0) },