PCI_BASE_ADDRESS_2
ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_2, 0x00000000);
pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
case PCI_BASE_ADDRESS_2:
case PCI_BASE_ADDRESS_2:
intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0);
pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_2, &data32);
start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
P54U_WRITE(NET2280_BRG_CFG_U32, PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_2,
writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_2);
PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_2,
pci_read_config_dword(a->pcid, PCI_BASE_ADDRESS_2,
if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_2,
if (vfio_pci_core_range_intersect_range(pos, count, PCI_BASE_ADDRESS_2,
vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_2],
case PCI_BASE_ADDRESS_2:
pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);