MYPF_REG
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
lld->gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
lld->db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A));
csio_wr_reg32(hw, MBMSGRDYINTEN_F, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A));
cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
csio_wr_reg32(hw, PFCIM_F, MYPF_REG(PL_PF_INT_CAUSE_A));
MYPF_REG(SGE_PF_GTS_A));
MYPF_REG(SGE_PF_GTS_A));
MYPF_REG(SGE_PF_KDOORBELL_A));
MYPF_REG(SGE_PF_KDOORBELL_A));