NAND_CMD_SEQIN
CMD_1(NAND_CMD_SEQIN) |
nc->op.cmds[0] = NAND_CMD_SEQIN;
case NAND_CMD_SEQIN:
ctlcode |= NAND_CMD_SEQIN;
case NAND_CMD_SEQIN:
[NAND_CMD_SEQIN] = CMD_NOT_SUPPORTED,
} else if (command == NAND_CMD_SEQIN)
if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
case NAND_CMD_SEQIN:
case NAND_CMD_SEQIN: {
(NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
case NAND_CMD_SEQIN: {
(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_SEQIN <<
hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
case NAND_CMD_SEQIN:
ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
case NAND_CMD_SEQIN:
if (opcode1 == NAND_CMD_SEQIN && opcode2 == NAND_CMD_PAGEPROG)
NDCB0_CMD1(NAND_CMD_SEQIN) |
NDCB0_CMD1(NAND_CMD_SEQIN);
cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
case NAND_CMD_SEQIN:
NAND_OP_CMD(NAND_CMD_SEQIN, 0),
chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
if (command == NAND_CMD_SEQIN) {
case NAND_CMD_SEQIN:
case NAND_CMD_SEQIN:
case NAND_CMD_SEQIN:
case NAND_CMD_SEQIN:
writel(PL35X_SMC_ECC_CMD1_WRITE(NAND_CMD_SEQIN) |
PL35X_SMC_CMD_PHASE_CMD0(NAND_CMD_SEQIN);
if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
.command = COMMAND_INPUT_SEL_DMA | COMMAND_0(NAND_CMD_SEQIN) |
.command = COMMAND_INPUT_SEL_AHBS | COMMAND_0(NAND_CMD_SEQIN) |
case NAND_CMD_SEQIN:
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
case NAND_CMD_SEQIN:
set_cmd_regs(mtd, NAND_CMD_SEQIN,
set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1);
cmd2 |= NAND_CMD_SEQIN << CMD_BYTE1_SHIFT;