NAND_CMD_RESET
if (cmd != NAND_CMD_RESET)
case NAND_CMD_RESET:
[NAND_CMD_RESET] = CMD_NOT_SUPPORTED,
op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET &&
case NAND_CMD_RESET:
out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
case NAND_CMD_RESET:
ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
case NAND_CMD_RESET:
case NAND_CMD_RESET:
if (opcode == NAND_CMD_STATUS || opcode == NAND_CMD_RESET || opcode == NAND_CMD_READID)
if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
NAND_OP_CMD(NAND_CMD_RESET,
chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
case NAND_CMD_RESET:
case NAND_CMD_RESET:
case NAND_CMD_RESET:
case NAND_CMD_RESET:
if (byte == NAND_CMD_RESET) {
case NAND_CMD_RESET:
if (instr->ctx.cmd.opcode != NAND_CMD_RESET &&
case NAND_CMD_RESET:
case NAND_CMD_RESET: