NAND_CMD_READSTART
CMD_2(NAND_CMD_READSTART) |
nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
ctlcode |= NAND_CMD_READSTART << 8;
[NAND_CMD_READSTART] = CMD_NOT_SUPPORTED,
cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
case NAND_CMD_READSTART:
if (opcode1 == NAND_CMD_READ0 && opcode2 == NAND_CMD_READSTART)
NDCB0_CMD2(NAND_CMD_READSTART),
NDCB0_CMD2(NAND_CMD_READSTART);
nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
case NAND_CMD_READSTART:
case NAND_CMD_READSTART:
PL35X_SMC_ECC_CMD1_READ_END(NAND_CMD_READSTART) |
PL35X_SMC_CMD_PHASE_CMD1(NAND_CMD_READSTART) |
case NAND_CMD_READSTART:
instr->ctx.cmd.opcode != NAND_CMD_READSTART)
COMMAND_2(NAND_CMD_READSTART) | COMMAND_FIFO_SEL |
COMMAND_2(NAND_CMD_READSTART) | COMMAND_FIFO_SEL |
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT;