NAND_CMD_READ0
CMD_1(NAND_CMD_READ0) |
nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
case NAND_CMD_READ0:
case NAND_CMD_READ0:
[NAND_CMD_READ0] = CMD_NOT_SUPPORTED,
command = NAND_CMD_READ0;
} else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
case NAND_CMD_READ0:
fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
ifc_out32(NAND_CMD_READ0 <<
case NAND_CMD_READ0:
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
case NAND_CMD_READ0:
if (command == NAND_CMD_READ0)
ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0);
case NAND_CMD_READ0:
if (opcode1 == NAND_CMD_READ0 && opcode2 == NAND_CMD_READSTART)
NDCB0_CMD1(NAND_CMD_READ0) |
NDCB0_CMD1(NAND_CMD_READ0) |
cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
case NAND_CMD_READ0:
command = NAND_CMD_READ0;
command = NAND_CMD_READ0;
mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
case NAND_CMD_READ0:
NAND_OP_CMD(NAND_CMD_READ0, 0),
NAND_OP_CMD(NAND_CMD_READ0, 0),
NAND_OP_CMD(NAND_CMD_READ0, 0),
chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
NAND_OP_CMD(NAND_CMD_READ0, 0),
NAND_OP_CMD(NAND_CMD_READ0, 0),
chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
readcmd = NAND_CMD_READ0;
case NAND_CMD_READ0:
command = NAND_CMD_READ0;
case NAND_CMD_READ0:
case NAND_CMD_READ0:
case NAND_CMD_READ0:
PL35X_SMC_ECC_CMD1_READ(NAND_CMD_READ0) |
PL35X_SMC_CMD_PHASE_CMD0(NAND_CMD_READ0) |
case NAND_CMD_READ0:
instr->ctx.cmd.opcode != NAND_CMD_READ0 &&
.command = COMMAND_INPUT_SEL_DMA | COMMAND_0(NAND_CMD_READ0) |
.command = COMMAND_INPUT_SEL_AHBS | COMMAND_0(NAND_CMD_READ0) |
case NAND_CMD_READ0:
set_cmd_regs(mtd, NAND_CMD_READ0,
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
set_cmd_regs(mtd, NAND_CMD_READ0,
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
case NAND_CMD_READ0:
| NAND_CMD_READ0);
read_cmd = NAND_CMD_READ0;
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
cmd2 |= NAND_CMD_READ0 << CMD_BYTE1_SHIFT;