NAND_CMD_PAGEPROG
CMD_2(NAND_CMD_PAGEPROG) |
case NAND_CMD_PAGEPROG:
NAND_CMD_PAGEPROG))
[NAND_CMD_PAGEPROG] = CMD_NOT_SUPPORTED,
if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
case NAND_CMD_PAGEPROG:
if (command != NAND_CMD_PAGEPROG)
(NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
case NAND_CMD_PAGEPROG: {
if (command != NAND_CMD_PAGEPROG)
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
nand_fcr0 = ((NAND_CMD_PAGEPROG <<
case NAND_CMD_PAGEPROG: {
hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
case NAND_CMD_PAGEPROG:
case NAND_CMD_PAGEPROG:
if (opcode1 == NAND_CMD_SEQIN && opcode2 == NAND_CMD_PAGEPROG)
NDCB0_CMD2(NAND_CMD_PAGEPROG) |
nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
case NAND_CMD_PAGEPROG:
NAND_OP_CMD(NAND_CMD_PAGEPROG,
NAND_OP_CMD(NAND_CMD_PAGEPROG,
chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
case NAND_CMD_PAGEPROG:
case NAND_CMD_PAGEPROG:
case NAND_CMD_PAGEPROG:
case NAND_CMD_PAGEPROG:
PL35X_SMC_CMD_PHASE_CMD1(NAND_CMD_PAGEPROG) |
case NAND_CMD_PAGEPROG:
instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG &&
COMMAND_1(NAND_CMD_PAGEPROG) | COMMAND_FIFO_SEL |
COMMAND_1(NAND_CMD_PAGEPROG) | COMMAND_FIFO_SEL |
case NAND_CMD_PAGEPROG:
set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
if (command != NAND_CMD_PAGEPROG)
case NAND_CMD_PAGEPROG:
writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2);
cmd1 |= NAND_CMD_PAGEPROG << CMD_BYTE2_SHIFT;